# US 12,183,397 B2 · Memory circuits and devices, and methods thereof

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- Number: US 12,183,397 B2
- Document ID: US12183397B2
- Status: Granted
- Kind: B2
- Application number: 17/644,794
- Filed: 2021-12-17
- Published: 2022-11-17
- Granted: 2024-12-31
- Earliest claimed: 2021-05-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yih Wang; Tung-Cheng Chang; Perng-Fei Yuh; Gu-Huan Li; Chia-En Huang; Chun-Ying Lee
- Web page: https://patentgrep.com/patent/US12183397B2

## CPC

- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 17/16: using electrically-fusible links
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

## Claims

### Claim 1

A memory circuit, comprising:
a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line; wherein:
a first of the bitcells and a second of the bitcells are coupled to a first of the bitlines;
the first bitcell is separately coupled to a first of the source lines and the control line; and
the second bitcell is separately coupled to a second of the source lines and the control line;
wherein:
the first source line is different from the second source line;
the first bitcell comprises a first transistor;
the second bitcell comprises a second transistor; and
the first transistor is coupled to the second transistor through a connection line, the connection line configured to float.

### Claim 2 (depends on 1)

The memory circuit of claim 1, wherein:
the first bitcell is coupled to a first of the wordlines and to the control line; and
the second bitcell is coupled to a second of the wordlines and to the control line.

### Claim 3 (depends on 2)

The memory circuit of claim 2, wherein:
the first transistor comprises a first gate coupled to a first power line for a first voltage level, the first voltage level to switch off the first transistor; and
the second transistor comprises a second gate coupled to a second power line for a second voltage level, the second voltage level to switch off the second transistor.

### Claim 4 (depends on 3)

The memory circuit of claim 3, wherein:
the first transistor comprises a first source, the first source configured to float; and
the second transistor comprises a second source, the second source configured to float.

### Claim 5 (depends on 3)

The memory circuit of claim 3, wherein:
a third of the bitcells and a fourth of the bitcells are coupled to a second of the bitlines;
the third bitcell is coupled to the first source line;
the fourth bitcell is coupled to the second source line;
the third bitcell is separately coupled to the first source line and the control line; and
the fourth bitcell is separately coupled to the second source line and the control line.

### Claim 6 (depends on 5)

The memory circuit of claim 5, wherein:
the third bitcell comprises a third transistor, the third transistor comprising a third gate coupled to the first power line for the first voltage level, the first voltage level to switch off the third transistor; and
the fourth bitcell comprises a fourth transistor, the fourth transistor comprising a fourth gate coupled to the second power line for the second voltage level, the second voltage level to switch off the fourth transistor.

### Claim 7 (depends on 6)

The memory circuit of claim 6, wherein:
the connection line is a first connection line, and
the third transistor is coupled to the fourth transistor through a second connection line, the second connection line configured to float.

### Claim 8 (depends on 1)

The memory circuit of claim 1, wherein the first bitcell comprises:
a capacitor coupled to the first bitline;
the first transistor coupled to the capacitor and the control line; and
a third transistor coupled to the first transistor, a first of the wordlines, and the first source line.

### Claim 9 (depends on 8)

The memory circuit of claim 8, wherein the first bitcell further comprises:
a fourth transistor coupled to the third transistor and comprising:
a gate coupled to a power line for a voltage level, the voltage level to switch off the fourth transistor; and
a source configured to float.

### Claim 10 (depends on 8)

The memory circuit of claim 8, wherein:
the first transistor comprises a first plurality of transistors coupled to the capacitor and the control line; and
the third transistor comprises a second plurality of transistors coupled to the first plurality of transistors, the first wordline, and the first source line.

### Claim 11 (depends on 1)

The memory circuit of claim 1, wherein:
the first source line is configured for a source-line signal of a voltage level, the voltage level being higher than a ground level of voltage.

### Claim 12 (depends on 11)

The memory circuit of claim 11, wherein:
the first bitcell comprises a capacitor;
the voltage level is a first voltage level;
the first bitline has a second voltage level;
a voltage difference equals the second voltage level minus the first voltage level; and
the voltage difference is not greater than a breakdown voltage of the capacitor.

### Claim 13 (depends on 1)

The memory circuit of claim 1, wherein:
the first bitcell comprises a first oxide diffusion (OD) layer;
the second bitcell comprises a second OD layer; and
the first OD layer is connected to the second OD layer.

### Claim 14 (depends on 1)

The memory circuit of claim 1, wherein:
the first bitcell comprises a first oxide diffusion (OD) layer;
the second bitcell comprises a second OD layer; and
the first OD layer is separate from the second OD layer.

### Claim 15

A memory device, comprising:
a plurality of bitcells coupled to a bitline, a plurality of wordlines, a plurality of source lines, and a control line; wherein:
ones of the plurality of bitcells are coupled to one of the source lines and separately coupled to the control line; and
the one of the source lines is configured for a source-line signal of a voltage level higher than a ground level of voltage,
wherein:
a first one of the plurality of bitcells comprises a first transistor;
a second one of the plurality of bitcells comprises a second transistor; and
the first transistor is coupled to the second transistor through a connection line, wherein the connection line is not the bitline and is configured to float.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein:
the ones of the plurality of bitcells are a first plurality of the bitcells;
the one of the source lines is a first source line;
the source-line signal is a first source-line signal;
the voltage level is a first voltage level;
a second plurality of the bitcells are coupled to a second of the source lines; and
the second source line is configured for a second source-line signal of a second voltage level higher than the ground level of voltage.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein:
the first plurality of the bitcells are coupled to first ones of the plurality of the wordlines; and
the second plurality of the bitcells are coupled to second ones of the plurality of the wordlines.

### Claim 18

A method for a memory circuit, wherein the memory circuit comprises a bitcell, the bitcell comprises a first transistor and a second transistor, and a drain of the first transistor is coupled to a source of the second transistor, the method comprising:
supplying a first signal of a first voltage level to a gate of the first transistor, the first voltage level to switch off the first transistor;
supplying a second signal of a second voltage level to a gate of the second transistor, the second voltage level to switch off the second transistor; and
supplying, from a source line, a third signal of a third voltage level to a connection point between the drain of the first transistor and the source of the second transistor, the third voltage level being higher than a ground level of voltage.

### Claim 19 (depends on 18)

The method of claim 18, wherein the bitcell further comprises a third transistor, the method further comprising:
supplying a fourth signal of a fourth voltage level to a gate of the third transistor, the fourth voltage level to switch on the third transistor.

### Claim 20 (depends on 18)

The method of claim 18, wherein the bitcell further comprises a capacitor, the method further comprising:
supplying a fourth signal of a fourth voltage level to a terminal of the capacitor, wherein:
a voltage difference equals the fourth voltage level minus the third voltage level; and
the voltage difference is not greater than a breakdown voltage of the capacitor.