# US 12,183,396 B2 · Memory array structures and methods of forming memory array structures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,396 B2
- Document ID: US12183396B2
- Status: Granted
- Kind: B2
- Application number: 18/096,072
- Filed: 2023-01-12
- Published: 2023-06-01
- Granted: 2024-12-31
- Earliest claimed: 2019-12-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dan Xu; Jun Xu; Erwin E. Yu; Paolo Tessariol; Tomoko Ogura Iwasaki
- Web page: https://patentgrep.com/patent/US12183396B2

## CPC

- G11C 13/003: {Cell access}
- G11C 29/025: {in signal lines}
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 13/0038: {Power supply circuits}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/54: Arrangements for designing test circuits, e.g. design for test [DFT] tools
- G11C 2029/1202: {Word line control}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

## Claims

### Claim 1

A memory array structure, comprising:
a first conductive plate connected to control gates of a first plurality of memory cells of a first dummy block of memory cells on a first side of a first isolation region, and further connected to control gates of a first plurality of memory cells of a second dummy block of memory cells on a second side of the first isolation region;
a second conductive plate connected to control gates of a second plurality of memory cells of the first dummy block of memory cells on a first side of a second isolation region, and further connected to control gates of a second plurality of memory cells of the second dummy block of memory cells on a second side of the second isolation region;
a first conductor connected to the first conductive plate through a first contact on the first side of the first isolation region, and selectively connected to a first global access line through a first block select transistor;
a second conductor connected to the first conductive plate through a second contact on the second side of the first isolation region, and selectively connected to the first global access line through a second block select transistor;
a third conductor connected to the second conductive plate through a third contact on the first side of the second isolation region, and selectively connected to a second global access line through a third block select transistor;
a fourth conductor connected to the second conductive plate through a fourth contact on the second side of the second isolation region, and selectively connected to the second global access line through a fourth block select transistor; and
a fifth conductor connected to the third conductor and connected to the second conductor.

### Claim 2 (depends on 1)

The memory array structure of claim 1, wherein the first isolation region extends less than a full length of the first conductive plate, and wherein the second isolation region extends less than a full length of the second conductive plate.

### Claim 3 (depends on 2)

The memory array structure of claim 2, wherein the first isolation region extends a majority of the length of the first conductive plate, and wherein the second isolation region extends a majority of the length of the second conductive plate.

### Claim 4 (depends on 1)

The memory array structure of claim 1, wherein the second conductive plate is overlying the first conductive plate, and wherein the first conductor, the second conductor, the third conductor, the fourth conductor, and the fifth conductor are each overlying the second conductive plate at a same level.

### Claim 5 (depends on 4)

The memory array structure of claim 4, wherein the second conductive plate is overlying less than all of the first conductive plate in a staircase structure.

### Claim 6 (depends on 4)

The memory array structure of claim 4, further comprising:
a third conductive plate connected to control gates of a third plurality of memory cells of the first dummy block of memory cells on a first side of a third isolation region, and further connected to control gates of a third plurality of memory cells of the second dummy block of memory cells on a second side of the third isolation region;
a sixth conductor connected to the third conductive plate through a fifth contact on the first side of the third isolation region, and selectively connected to a third global access line through a fifth block select transistor;
a seventh conductor connected to the third conductive plate through a sixth contact on the second side of the third isolation region, and selectively connected to the third global access line through a seventh block select transistor; and
an eighth conductor connected to the sixth conductor and connected to the fourth conductor.

### Claim 7 (depends on 6)

The memory array structure of claim 6, wherein the third conductive plate is overlying the second conductive plate, and wherein the sixth conductor, the seventh conductor, and the eighth conductor are each overlying the third conductive plate at the same level as the first conductor, the second conductor, the third conductor, the fourth conductor, and the fifth conductor.

### Claim 8 (depends on 7)

The memory array structure of claim 7, wherein the third conductive plate is overlying less than all of the second conductive plate in the staircase structure.

### Claim 9 (depends on 1)

The memory array structure of claim 1, further comprising:
a first driver circuitry for access of a memory cell of the first dummy block of memory cells and comprising the first block select transistor and the third block select transistor; and
a second driver circuitry for access of a memory cell of the second dummy block of memory cells and comprising the second block select transistor and the fourth block select transistor.

### Claim 10

A memory array structure, comprising:
a first block of memory cells including a first plurality of local access lines, wherein each local access line of the first plurality of local access lines is connected to control gates of a respective plurality of memory cells of the first block of memory cells, and wherein each local access line of the first plurality of local access lines is selectively connected to a respective global access line of a plurality of global access lines through a respective selective connection of a first plurality of selective connections;
a second block of memory cells including a second plurality of local access lines, wherein each local access line of the second plurality of local access lines is connected to control gates of a respective plurality of memory cells of the second block of memory cells, and wherein each local access line of the second plurality of local access lines is selectively connected to the respective global access line of a corresponding local access line of the first plurality of local access lines through a respective selective connection of a second plurality of selective connections; and
a current path as a direct electrical connection between a particular local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines;
wherein the first plurality of selective connections are selectively activated independently from the second plurality of selective connections.

### Claim 11 (depends on 10)

The memory array structure of claim 10, wherein the current path is a first current path, and wherein the memory further comprises:
a second current path as a direct electrical connection between the particular local access line of the first plurality of local access lines and a different local access line of the second plurality of local access lines in a different physical plane than the particular local access line of the first plurality of local access lines.

### Claim 12 (depends on 10)

The memory array structure of claim 10, wherein the current path is in a same physical plane as the particular local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines.

### Claim 13 (depends on 10)

The memory array structure of claim 10, wherein the control gates of the respective plurality of memory cells of the first block of memory cells for the particular local access line of the first plurality of local access lines are between the current path and the respective selective connection of the first plurality of selective connections for the particular local access line of the first plurality of local access lines.

### Claim 14 (depends on 10)

The memory array structure of claim 10, wherein, for each local access line of the first plurality of local access lines, the memory array structure further comprises:
a respective current path as a direct electrical connection between that local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines.

### Claim 15

A memory array structure, comprising:
a first block of memory cells including a first plurality of local access lines, wherein each local access line of the first plurality of local access lines is connected to control gates of a respective plurality of memory cells of the first block of memory cells;
a second block of memory cells including a second plurality of local access lines, wherein each local access line of the second plurality of local access lines is connected to control gates of a respective plurality of memory cells of the second block of memory cells, and wherein each local access line of the second plurality of local access lines is in a same physical plane as a corresponding local access line of the first plurality of local access lines;
a current path between a particular local access line of the first plurality of local access lines and its corresponding local access line of the second plurality of local access lines; and
a conductive plate having an isolation region extending less than a full length of the conductive plate;
wherein the particular local access line of the first plurality of local access lines comprises a first portion of the conductive plate on a first side of the isolation region, and wherein its corresponding local access line of the second plurality of local access lines comprises a second portion of the conductive plate on a second side of the isolation region; and
wherein the current path comprises a third portion of the conductive plate between an end of the isolation region and an edge of the conductive plate.

### Claim 16

A method of forming a memory array structure, comprising:
forming a first conductive plate;
forming a second conductive plate overlying the first conductive plate;
forming a first isolation region in the first conductive plate and extending less than a full length of the first conductive plate;
forming a second isolation region in the second conductive plate and extending less than a full length of the second conductive plate;
forming a first contact connected to the first conductive plate on a first side of the first isolation region;
forming a second contact connected to the first conductive plate on a second side of the first isolation region;
forming a third contact connected to the second conductive plate on a first side of the second isolation region;
forming a fourth contact connected to the second conductive plate on a second side of the second isolation region; and
forming a conductor connected to the third contact and connected to the second contact;
wherein the first conductive plate forms control gates of a first plurality of memory cells of a first block of memory cells and forms control gates of a first plurality of memory cells of a second block of memory cells; and
wherein the second conductive plate forms control gates of a second plurality of memory cells of the first block of memory cells and forms control gates of a second plurality of memory cells of the second block of memory cells.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the second conductive plate overlying the first conductive plate comprises forming the second conductive plate overlying less than all of the first conductive plate.

### Claim 18 (depends on 16)

The method of claim 16, wherein the first conductive plate forms control gates of the first plurality of memory cells of the first block of memory cells on the first side of the first isolation region and forms control gates of the first plurality of memory cells of the second block of memory cells on the second side of the first isolation region, and wherein the second conductive plate forms control gates of the second plurality of memory cells of the first block of memory cells on the first side of the second isolation region and forms control gates of the second plurality of memory cells of the second block of memory cells on the second side of the second isolation region.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the third contact connected to the second conductive plate on the first side of the second isolation region comprises forming the third contact to extend from an upper surface of the second conductive plate on the first side of the second isolation region to a particular level above the upper surface of the second conductive plate, wherein forming the fourth contact connected to the second conductive plate on the second side of the second isolation region comprises forming the fourth contact to extend from the upper surface of the second conductive plate on the second side of the second isolation region to the particular level, wherein forming the first contact connected to the first conductive plate on the first side of the first isolation region comprises forming the first contact to extend from an upper surface of the first conductive plate on the first side of the first isolation region to the particular level, and wherein forming the second contact connected to the first conductive plate on the second side of the first isolation region comprises forming the second contact to extend from the upper surface of the first conductive plate on the second side of the first isolation region to the particular level.

### Claim 20 (depends on 19)

The method of claim 19, wherein the conductor is a fifth conductor, and wherein the method further comprises:
forming a first conductor connected to the first contact at the particular level;
forming a second conductor connected to the second contact at the particular level;
forming a third conductor connected to the third contact at the particular level;
forming a fourth conductor connected to the fourth contact at the particular level; and
forming the fifth conductor connected to the third conductor and the second conductor at the particular level.