Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

A method of operating a neural network accelerator system, comprising:

• coupling a plurality of non-volatile memory (NVM) devices via a bus system, wherein each NVM device includes multi-level memory cells;
• writing one of N×analog weight values to the multi-level memory cells of the plurality of NVM devices, wherein each analog weight value corresponds to a target drain current (ID) range extending from a target ID lower limit (LL) to a target ID upper limit (UL) and N is a natural number greater than 2, wherein writing the one of N×analog weight values includes a fine-tuning operation comprising performing a series of partial program, partial erase, and verification read operations, wherein the fine-tuning operation further includes a first verification read operation after the partial program operation to determine how a reduced ID level of a first multi-level memory cell is compared to a target ID mean, a second verification read operation after the partial erase operation to determine how a raised ID level is compared to the target ID mean, and wherein the writing one of N×analog weight values to the first memory cell is determined to be completed when an ID level of the first multi-level memory cell falls within the target ID range;
• providing inputs to at least one NVM device through the bus system;
• performing multiply accumulate (MAC) operations based on the inputs and the one of the N×analog weight values stored in the multi-level memory cells of the at least one NVM device;
• and
• transmitting the outputs from a first NVM device of the at least one NVM device as inputs to a second NVM device, via the bus system.

A semiconductor inference device, comprising:

• a non-volatile memory (NVM) array including multi-level memory cells, wherein each multi-level memory cell is configured to store one of N×analog values corresponding to N×levels of one of its electrical properties, wherein each electrical properties level corresponds to a target range extending from a target lower limit (LL) to a target upper limit (UL), wherein the N×analog values stored represent N×weight values for multiply accumulate (MAC) operations, N being a natural number greater than 2, wherein the one of N×analog weight values is written with a fine-tuning operation comprising performing a series of partial program, partial erase, and verification read operations, wherein the fine-tuning operation further includes a first verification read operation after the partial program operation to determine how a reduced electrical properties level of a first multi-level memory cell is compared to a target ID mean, a second verification read operation after the partial erase operation to determine how a raised electrical properties level is compared to the target ID mean, and wherein the writing one of N×analog weight values to the first multi-level memory cell is determined to be completed when an electrical properties level of the first multi-level memory cell falls within the target range;
• digital-to-analog (DAC) function configured to receive and convert digital inputs from external devices, wherein each digital input is configured to cause a weight value stored in at least one multi-level memory cell selected to be read;
• multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results;
• and
• analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value and output the digital value.