# US 12,183,393 B2 · High-speed multi-port memory supporting collision

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- Number: US 12,183,393 B2
- Document ID: US12183393B2
- Status: Granted
- Kind: B2
- Application number: 18/603,118
- Filed: 2024-03-12
- Published: 2024-07-04
- Granted: 2024-12-31
- Earliest claimed: 2021-03-23
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Pradeep Raj; Rahul Sahu; Sharad Kumar Gupta
- Web page: https://patentgrep.com/patent/US12183393B2

## CPC

- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 11/418: Address circuits
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

## Claims

### Claim 1

A multi-port memory, comprising:
a multi-port bitcell including a first read port having a first read port bit line and a first read port word line, the multi-port bitcell further including a write port having a pair of write bit lines;
an address comparator configured to detect a collision responsive to a write port address being directed to the write port and a read port address being directed to the first read port;
a read port word line controller configured to assert the first read port word line responsive to a lack of a detection of the collision and configured to not assert the first read port word line responsive to a detection of the collision;
a sense amplifier configured to perform a differential read through the write port responsive to the write port address being directed to the write port;
an inverter coupled to the first read port bit line; and
a multiplexer configured to select between an output of the inverter and the sense amplifier.

### Claim 2 (depends on 1)

The multi-port memory of claim 1, wherein the read port word line controller is further configured to assert a pre-charge signal for the first read port responsive to the lack of the detection of the collision, and wherein the first read port is further configured to float the first read port bit line responsive to an assertion of the pre-charge signal.

### Claim 3 (depends on 1)

The multi-port memory of claim 1, further comprising:
a data driver configured to drive the pair of write port bit lines with a data bit to be written to the multi-port bitcell after a completion of the differential read.

### Claim 4

A multi-port memory, comprising:
an address comparator configured to detect a collision responsive to a read port address and a write port address both being directed to a first multi-port bitcell;
a sense amplifier configured to read a first data bit from the first multi-port bitcell through a write port;
a write driver configured to write a second data bit to the first multi-port bitcell through the write port after a completion of the read of the first data bit;
a multiplexer coupled to the sense amplifier, the multiplexer configured to select for the first data bit responsive to a detection of the collision; and
an inverter coupled to a read port bit line in a first read port in the first multi-port bitcell, wherein the multiplexer is further configured to select for an output of the inverter responsive to a detection of a lack of the collision.

### Claim 5 (depends on 4)

The multi-port memory of claim 4, further comprising:
a data latch configured to latch an output bit from the multiplexer.

### Claim 6 (depends on 4)

The multi-port memory of claim 4, wherein the first multi-port bitcell includes a second read port.

### Claim 7 (depends on 4)

The multi-port memory of claim 4, further comprising:
a read port word line controller configured to assert a word line to the first read port responsive to the detection of the lack of the collision.

### Claim 8 (depends on 7)

The multi-port memory of claim 7, wherein the read port word line controller is further configured to assert a pre-charge signal to the first read port responsive to the detection of the lack of the collision.

### Claim 9 (depends on 4)

The multi-port memory of claim 4, wherein the address comparator is configured to be triggered to detect the collision responsive to an edge of a clock signal.