# US 12,183,385 B2 · Apparatuses and methods for a per-DRAM addressability synchronizer circuit

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- Number: US 12,183,385 B2
- Document ID: US12183385B2
- Status: Granted
- Kind: B2
- Application number: 17/890,974
- Filed: 2022-08-18
- Published: 2024-02-22
- Granted: 2024-12-31
- Earliest claimed: 2022-08-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: William C. Waldrop; Liang Chen; Shingo Mitsubori; Ryo Fujimaki; Atsuko Momma
- Web page: https://patentgrep.com/patent/US12183385B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/1093: {Input synchronization}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

## Claims

### Claim 1

An apparatus comprising:
a delay circuit configured to receive a first per DRAM addressability (PDA) signal and output a second PDA signal which is delayed from the first PDA signal;
a synchronizer circuit configured to receive the first PDA signal and a DQS clock signal and output a third PDA signal synchronous to the DQS clock signal; and
a logic circuit configured to output one of the second PDA signal and the third PDA signal at an output node thereof.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising an additional logic circuit configured to output the first PDA signal responsive to a write control signal and a PDA enable signal.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the logic circuit is configured to output the one of the second PDA signal and the third PDA signal at the output node thereof when the PDA enable signal is received and output the write control signal at the output node thereof when the PDA enable signal is not received.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the delay circuit is configured to provide the second PDA signal when the PDA enable signal is not received.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising a data latch configured to begin receiving data with timing based on the DQS clock signal responsive to the first PDA signal.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first PDA signal is synchronous to the DQS clock signal as part of a first mode and asynchronous to the DQS clock signal as part of a second mode.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the delay circuit is configured to provide the second PDA signal before the synchronizer circuit provides the third PDA signal as part of the first mode, and wherein the synchronizer circuit is configured to provide the third PDA signal before the delay circuit provides the second PDA signal as part of the second mode.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
enabling data latches based, in part on the synchronized write control signal; and
receiving data at the data latches with timing based on the DQS clock signal.

### Claim 9

A method comprising:
generating an asynchronous first per DRAM addressability (PDA) signal responsive to a PDA enable signal at an active level and a write control signal as part of a PDA operation;
delaying the first PDA signal by a delay time to provide a second PDA signal;
synchronizing the first PDA signal to a DQS clock signal to provide a third PDA signal; and
providing a synchronized write control signal responsive to the second PDA signal or the third PDA signal.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
receiving the PDA enable signal at an inactive level and the write start signal as part of a write operation; and
providing the write start signal as the synchronized write control signal when the PDA enable signal is inactive.

### Claim 11 (depends on 10)

The method of claim 10, further comprising providing the second PDA signal responsive to the PDA enable signal at the inactive level.

### Claim 12 (depends on 9)

The method of claim 9, further comprising receiving a PDA command as a multi-purpose command to begin the PDA operation.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
receiving the write control signal synchronous to the DQS clock as part of a first mode; and
receiving the write control signal asynchronous to the DQS clock as part of a second mode.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
providing the second PDA signal before providing the third PDA signal as part of the first mode;
providing the third PDA signal before the second PDA signal as part of the second mode.