# US 12,183,384 B2 · Information processing apparatus, information processing system, and semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,384 B2 - Document ID: US12183384B2 - Status: Granted - Kind: B2 - Application number: 18/426,905 - Filed: 2024-01-30 - Published: 2024-06-13 - Granted: 2024-12-31 - Earliest claimed: 2019-04-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Akihisa Fujimoto; Atsushi Kondo - Web page: https://patentgrep.com/patent/US12183384B2 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G06F 3/0614: {Improving the reliability of storage systems} - G06F 3/0625: {Power saving in storage systems} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 16/20: Initialising; Data preset; Chip identification - G11C 16/30: Power supply circuits - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position. ## Claims ### Claim 1 An information processing system comprising a host device and a semiconductor storage device capable of being placed into the host device, wherein the semiconductor storage device comprises: a housing having a first surface, a second surface located on a side opposite to the first surface, a first end edge extending in a first direction, a second end edge located on a side opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion being between the first end edge and the first side edge; a nonvolatile memory; a controller being connected to the nonvolatile memory; and a plurality of terminals provided on the first surface, the plurality of terminals of the semiconductor storage device include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals, the first plurality of terminals are arranged in the first direction at a position closer to the first end edge than the second end edge, the third plurality of terminals are arranged in the first direction at a position closer to the second end edge than the first end edge, the second plurality of terminals are arranged between the first plurality of terminals and the third plurality of terminals in the first direction, the first plurality of terminals are closer to the first end edge than the second plurality of terminals are, the first plurality of terminals include at least one pair of first signal terminals for differential data signals, the differential data signals complying with PCIe standard, the first plurality of terminals include a first plurality of ground terminals assigned to ground, each pair of the at least one pair of first signal terminals is located between two of the first plurality of ground terminals, the second plurality of terminals include a second plurality of ground terminals assigned to ground, the third plurality of terminals include differential clock signal terminals assigned to differential clock signals having a frequency lower than that of the differential data signals, a first and second terminals, each of the first and the second terminals being assigned to a single-end signal, a first power supply terminal assigned to a first power supply, and a second power supply terminal assigned to a second power supply having a voltage equal to or lower than that of the first power supply, the host device has a connector into which the semiconductor storage device is capable of being placed, and the host device is configured to supply the first power supply to the first power supply terminal, supply the second power supply to the second power supply terminal, supply a reference clock signal to the differential clock signal terminals, when a clock request signal from the first terminal is Low after a period since the first power supply and second power supply are supplied to the semiconductor storage device reaches a first time, and supply a High signal to the second terminal after a period since the reference clock signal are supplied reaches a second time. ### Claim 2 (depends on 1) The information processing system according to claim 1, wherein the housing has a second side edge located on a side opposite to the first side edge and extending in the second direction, and a second corner portion being between the first end edge and the second side edge, and shapes of the first corner portion and the second corner portion are different from each other. ### Claim 3 (depends on 2) The information processing system according to claim 2, wherein each of the first terminal and the second terminal is assigned to sideband signals of PCIe standard. ### Claim 4 (depends on 3) The information processing system according to claim 3, wherein the number of the first plurality of terminals is equal to the number of the third plurality of terminals. ### Claim 5 (depends on 4) The information processing system according to claim 4, wherein the connector includes a plurality of lead frames, and the host device is configured to supply the first power supply to the first power supply terminal and supply the second power supply to the second power supply terminal, through the plurality of lead frames. ### Claim 6 (depends on 2) The information processing system according to claim 2, wherein the semiconductor storage device includes a voltage detector, the semiconductor storage device is configured to drive the clock request signal to Low so as to request the reference clock signal when the voltage detector detects the supplied first power supply and the supplied second power supply. ### Claim 7 (depends on 2) The information processing system according to claim 2, wherein the host device is configured to check whether or not a notch is formed at a predetermined position of the first side edge in the semiconductor storage device placed into the connector, and supply the first power supply and the second power supply to the semiconductor storage device placed into the connector, when the notch is formed at the predetermined position of the first side edge in the semiconductor storage device placed into the connector. ### Claim 8 (depends on 7) The information processing system according to claim 7, wherein the host device is configured to not supply the first power supply and the second power supply to the semiconductor storage device placed into the connector, when the notch is not formed at the predetermined position of the first side edge in the semiconductor storage device placed into the connector. ### Claim 9 (depends on 2) The information processing system according to claim 2, wherein the semiconductor storage device is configured to start an initialization sequence after the High signal is supplied to the second terminal. ### Claim 10 (depends on 2) The information processing system according to claim 2, wherein a power supply voltage of the first power supply is 2.5V. ### Claim 11 A host device having a connector into which a semiconductor storage device is capable of being placed, wherein the semiconductor storage device comprises: a housing having a first surface, a second surface located on a side opposite to the first surface, a first end edge extending in a first direction, a second end edge located on a side opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion being between the first end edge and the first side edge; a nonvolatile memory; a controller being connected to the nonvolatile memory; and a plurality of terminals provided on the first surface, the plurality of terminals of the semiconductor storage device include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals, the first plurality of terminals are arranged in the first direction at a position closer to the first end edge than the second end edge, the third plurality of terminals are arranged in the first direction at a position closer to the second end edge than the first end edge, the second plurality of terminals are arranged between the first plurality of terminals and the third plurality of terminals in the first direction, the first plurality of terminals are closer to the first end edge than the second plurality of terminals are, the first plurality of terminals include at least one pair of first signal terminals for differential data signals, the differential data signals complying with PCIe standard, the first plurality of terminals include a first plurality of ground terminals assigned to ground, each pair of the at least one pair of first signal terminals is located between two of the first plurality of ground terminals, the second plurality of terminals include a second plurality of ground terminals assigned to ground, the third plurality of terminals include differential clock signal terminals assigned to differential clock signals having a frequency lower than that of the differential data signals, a first and second terminals, each of the first and the second terminals being assigned to a single-end signal, a first power supply terminal assigned to a first power supply, and a second power supply terminal assigned to a second power supply having a voltage equal to or lower than that of the first power supply, when the semiconductor storage device is placed into the connector, the host device is configured to supply the first power supply to the first power supply terminal, supply the second power supply to the second power supply terminal, supply a reference clock signal to the differential clock signal terminals when a clock request signal from the first terminal is Low after a period since the first power supply and second power supply are supplied to the semiconductor storage device reaches a first time, and supply a High signal to the second terminal after a period since the reference clock signal are supplied reaches a second time. ### Claim 12 (depends on 11) The host device according to claim 11, wherein the housing has a second side edge located on a side opposite to the first side edge and extending in the second direction, and a second corner portion being between the first end edge and the second side edge, and shapes of the first corner portion and the second corner portion are different from each other. ### Claim 13 (depends on 12) The host device according to claim 12, wherein each of the first terminal and the second terminal is assigned to sideband signals of PCIe standard. ### Claim 14 (depends on 13) The host device according to claim 13, wherein the number of the first plurality of terminals is equal to the number of the third plurality of terminals. ### Claim 15 (depends on 14) The host device according to claim 14, wherein the connector includes a plurality of lead frames, and the host device is configured to supply the first power supply to the first power supply terminal and supply the second power supply to the second power supply terminal, through the plurality of lead frames. ### Claim 16 (depends on 12) The host device according to claim 12, wherein the semiconductor storage device includes a voltage detector, the semiconductor storage device is configured to drive the clock request signal to Low so as to request the reference clock signal when the voltage detector detects the supplied first power supply and the supplied second power supply. ### Claim 17 (depends on 12) The host device according to claim 12, wherein the host device is configured to check whether or not a notch is formed at a predetermined position of the first side edge in the semiconductor storage device placed into the connector, and supply the first power supply and the second power supply to the semiconductor storage device placed into the connector, when the notch is formed at the predetermined position of the first side edge in the semiconductor storage device placed into the connector. ### Claim 18 (depends on 17) The host device according to claim 17, wherein the host device is configured to not supply the first power supply and the second power supply to the semiconductor storage device placed into the connector, when the notch is not formed at the predetermined position of the first side edge in the semiconductor storage device placed into the connector. ### Claim 19 (depends on 12) The host device according to claim 12, wherein the semiconductor storage device is configured to start an initialization sequence after the High signal is supplied to the second terminal. ### Claim 20 (depends on 12) The host device according to claim 12, wherein a power supply voltage of the first power supply is 2.5V.