Apparatuses and methods for skipping wordline activation of defective memory during refresh operations

An apparatus, comprising:

• a plurality of rows of memory cells;
• and
• a row address control circuit configured to, during a refresh operation that includes a row hammer refresh followed by a second refresh;
• determine, during the row hammer refresh, a defective row of memory cells of the plurality of rows of memory cells;
• and
• skip a refresh in the defective row of memory cells while performing a refresh during the second refresh in a non-defective row of memory cells of the plurality of rows of memory cells,
• wherein the row address control circuit includes a redundancy match register circuit configured to determine whether one or more addresses have been replaced with a redundant address, and
• wherein the row address control circuit is configured to determine whether any of the plurality of rows have been replaced with the redundant row via the redundancy match register circuit, and based at least in part on a row being replaced with the redundant row, the row address control circuit is configured to prevent activation of the row determined to be replaced via a row selector.

A method, comprising:

• determining, during a row hammer refresh, a defective row of memory cells of a plurality of rows of memory cells;
• determining whether one or more addresses have been replaced with a redundant address;
• providing the one or more addresses to a redundancy match register circuit;
• providing one or more second refresh addresses and a select refresh address signal based at least in part on a refresh signal;
• determining whether any of the plurality of rows of memory cells have been replaced with a redundant row, and based at least in part on at least one row being replaced with the redundant row, preventing activation of the row determined to be replaced;
• and
• skipping a refresh in the defective row of memory cells while performing a second refresh in a non-defective row of memory cells of the plurality of rows of memory cells, wherein the second refresh follows the row hammer refresh.

A row address control circuit, comprising:

• a refresh region counter circuit;
• an address latch circuit;
• a first buffer circuit coupled to the refresh region counter circuit and the address latch circuit;
• a second buffer circuit coupled to the address latch circuit and the first buffer circuit;
• a pre-decoder circuit coupled to the address latch circuit;
• a redundancy match register circuit coupled to the first buffer, the second buffer, and the pre-decoder circuit;
• a latch circuit coupled to the refresh region counter circuit and the redundancy match register circuit;
• a row selector circuit coupled to the latch circuit and the pre-decoder circuit;
• and
• a row decoder circuit coupled to the row selector circuit and the pre-decoder circuit,
• wherein the redundancy match register circuit is configured to determine whether one or more addresses have been replaced with a redundant address and is further configured to provide an active signal to the latch circuit and the redundant address to the pre-decoder circuit when one or more addresses have been determined to be replaced with the redundant address.

A row address control circuit, comprising:

• a refresh region counter circuit;
• an address latch circuit;
• a first buffer circuit coupled to the refresh region counter circuit and the address latch circuit;
• a second buffer circuit coupled to the address latch circuit and the first buffer circuit;
• a pre-decoder circuit coupled to the address latch circuit;
• a redundancy match register circuit coupled to the first buffer, the second buffer, and the pre-decoder circuit;
• a latch circuit coupled to the refresh region counter circuit and the redundancy match register circuit;
• a row selector circuit coupled to the latch circuit and the pre-decoder circuit;
• and
• a row decoder circuit coupled to the row selector circuit and the pre-decoder circuit,
• wherein the refresh region counter circuit is configured to provide one or more second refresh addresses and a select refresh address signal to the first buffer circuit based at least in part on a refresh signal.

A row address control circuit, comprising:

• a refresh region counter circuit;
• an address latch circuit;
• a first buffer circuit coupled to the refresh region counter circuit and the address latch circuit;
• a second buffer circuit coupled to the address latch circuit and the first buffer circuit;
• a pre-decoder circuit coupled to the address latch circuit;
• a redundancy match register circuit coupled to the first buffer, the second buffer, and the pre-decoder circuit;
• a latch circuit coupled to the refresh region counter circuit and the redundancy match register circuit;
• a row selector circuit coupled to the latch circuit and the pre-decoder circuit;
• and
• a row decoder circuit coupled to the row selector circuit and the pre-decoder circuit,
• wherein the row decoder is configured to decode one or more signals to determine whether to perform or skip an access operation on a particular section of a corresponding memory bank.