# US 12,183,379 B2 · Enhancing tunnel magnetoresistance in memory device comprising a memory cell with a memory element coupled between a switch and a negative resistance device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,379 B2 - Document ID: US12183379B2 - Status: Granted - Kind: B2 - Application number: 17/994,407 - Filed: 2022-11-28 - Published: 2023-03-23 - Granted: 2024-12-31 - Earliest claimed: 2019-07-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wen-Chin Lin; Hung-Chang Yu - Web page: https://patentgrep.com/patent/US12183379B2 ## CPC - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/1655: {Bit-line or column circuits} - G11C 11/1657: {Word-line or row circuits} - G11C 11/1659: {Cell access} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided. ## Claims ### Claim 1 A memory device, comprising: at least one memory cell, wherein at least one memory cell comprising: a switch, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line; a memory element; and a negative resistance device, wherein the memory element is coupled between a second terminal of the switch and a first terminal of the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line, wherein during a read operation in the memory device, a read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state. ### Claim 2 (depends on 1) The memory device of claim 1, wherein a loading of the at least one memory cell is reduced while the negative resistance device is entering into the negative resistance state. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the negative resistance device is an ovonic threshold switch (OTS), and the switch is a CMOS transistor. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the memory element is a magnetic tunnel junction (MTJ) device. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the predetermined threshold voltage of the negative resistance device is adjusted with different materials. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the negative resistance device is a metal-semiconductor-metal (MSM). ### Claim 8 (depends on 6) The memory device of claim 6, wherein the negative resistance device is a mixed-ionic-electronic-conduction device (MIEC). ### Claim 9 (depends on 6) The memory device of claim 6, wherein the negative resistance device comprises at least one of the elements in a Chalcogenide group. ### Claim 10 (depends on 1) The memory device of claim 1, wherein during a write operation in the memory device, a write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state. ### Claim 11 A memory device, comprising: a driver configured to generate a read voltage and a write voltage to perform a read operation and a write operation in the memory device; a sense amplifier; a data output, configured to receive an input from the sense amplifier and generate an output; a memory cell array, wherein the memory cell array comprising: at least one memory cell, wherein the at least one memory cell comprising: a switch, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line; a memory element; and a negative resistance device, wherein the memory element is coupled between a second terminal of the switch and a first terminal of the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line, wherein during the read operation in the memory device, the read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state. ### Claim 12 (depends on 11) The memory device of claim 11, wherein a loading of the at least one memory cell is reduced while the negative resistance device is entering into the negative resistance state. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the negative resistance device is an ovonic threshold switch (OTS), the switch is a CMOS transistor, and the memory element is a magnetic tunnel junction (MTJ) device. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line. ### Claim 15 (depends on 11) The memory device of claim 11, wherein during the write operation in the memory device, the write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state. ### Claim 16 A method to control a memory cell in a memory device, comprising: determine whether the memory cell is in a read operation or not, wherein the memory cell includes a switch, a memory element, and a negative resistance device, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line, the memory element is coupled between the switch and the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line; and during the read operation of the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device to the negative resistance device for making the negative resistance device enter into a negative resistance state. ### Claim 17 (depends on 16) The method of claim 16, wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line. ### Claim 18 (depends on 16) The method of claim 16, further comprising: determine whether the memory cell is in a write operation or not; wherein during the write operation, apply a write voltage greater than the predetermined threshold voltage to the negative resistance device for making the negative resistance device enter into a low resistance state.