# US 12,183,303 B2 · Display device

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- Number: US 12,183,303 B2
- Document ID: US12183303B2
- Status: Granted
- Kind: B2
- Application number: 18/544,552
- Filed: 2023-12-19
- Published: 2024-05-09
- Granted: 2024-12-31
- Earliest claimed: 2015-10-30
- Assignees: Japan Display Inc.
- Applicants: Japan Display Inc.
- Inventors: Takayuki Suzuki; Hiroyuki Abe
- Web page: https://patentgrep.com/patent/US12183303B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G02F 1/1345: Conductors connecting electrodes to cell terminals
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 2201/56: Substrates having a particular shape, e.g. non-rectangular
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

## Claims

### Claim 1

A display device comprising a substrate on which a display region and a peripheral region having a scanning line drive circuit, wherein:
the scanning line drive circuit includes a plurality of clock wirings and a VDD wiring, a VSS wiring, and a plurality of unit circuits,
the plurality of unit circuits are provided between the VDD wiring and the VSS wiring at the peripheral region in a plan view,
the VSS wiring is provided between the plurality of unit circuits and the display region in the plan view,
the plurality of clock wirings is provided between the VDD wiring and an end of the substrate in the plan view, and
none of the plurality of clock wiring is provided between the VDD wiring and the plurality of unit circuits in the plan view,
wherein
the plurality of unit circuits have a first unit circuit and a second unit circuit adjacent to the first unit circuit in a direction along the end of the substrate,
the first unit circuit and the second unit circuit are connected via a coupling wiring,
the coupling wiring is provided between the VDD wiring and the VSS wiring in the plan view,
the clock wirings have a first clock wiring,
the first clock wiring is connected to the first unit circuit by a first connection wiring, and
the first connection wiring intersects the VDD wiring,
the first connection wiring has a first part and a second part,
the first part extends parallel to the first clock wiring directly above the first clock wiring, and
the second part extends from the first part to be connected to the first circuit and passes across the VDD wiring.

### Claim 2 (depends on 1)

The display device of claim 1, wherein
a width of the VDD wiring is smaller than a width of the VSS wiring.

### Claim 3 (depends on 1)

The display device of claim 1, wherein
a common wiring is provided between the VSS wiring and the display region.

### Claim 4 (depends on 3)

The display device of claim 3, wherein
a width of the VDD wiring is smaller than a width of the VSS wiring, and
a width of the common wiring is larger than the width of the VSS wiring.

### Claim 5 (depends on 1)

The display device of claim 1, wherein
none of the plurality of clock wiring is provided between the VSS wiring and the plurality of unit circuits in the plan view,
the first connection wiring does not intersect the VSS wiring.