# US 12,183,266 B1 · Gate driving circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,266 B1 - Document ID: US12183266B1 - Status: Granted - Kind: B1 - Application number: 18/282,921 - Filed: 2023-08-14 - Granted: 2024-12-31 - Earliest claimed: 2023-07-26 - Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Huanxi Zhang - Web page: https://patentgrep.com/patent/US12183266B1 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude. ## Claims ### Claim 1 A gate driving circuit, comprising a plurality of shift registers, wherein at least one of the plurality of shift registers comprises: a cascade signal selection module, electrically connected between a first wiring and a first node; a pull-up control module, configured to conduct a voltage level of a first node to the second node in response to a first clock signal; a first filter module, electrically connected between the second node and a third node, wherein a control end of the first filter module receives a reset signal; a second filter module, electrically connected between the first filter module and the third node, wherein a control end of the second filter module receives a filter control signal; a first inverting module, connected between the second node and a fourth node; a first output module, configured to output a first gate driving signal according to a voltage level of the third node and a voltage level of the fourth node; a second output module, comprising a P-type first transistor and an N-type second transistor, wherein a first electrode of the first transistor is electrically connected to a first high voltage line, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor to output a second gate driving signal, a second electrode of the second transistor is receives a first low voltage signal, the second node is electrically connected to a gate of the first transistor and a gate of the second transistor; and a voltage regulating module, receiving a low voltage signal and connected to the gate of the second transistor, wherein a control end of the voltage regulating module is electrically connected to one of the fourth node, an output end of the second output module and the first node of the shift register of a next stage. ### Claim 2 (depends on 1) The gate driving circuit of claim 1, wherein the voltage regulating module comprises a third transistor, a first electrode of the third transistor is connected to the low voltage signal, a second electrode of the third transistor is electrically connected to the gate of the second transistor, a gate of the third transistor is electrically connected to one of the fourth node, the output end of the second output module and the first node of the shift register of the next stage. ### Claim 3 (depends on 2) The gate driving circuit of claim 2, wherein the gate of the third transistor is electrically connected to one of the fourth node and the output end of the second output module, the low voltage signal is the first low voltage signal, and a channel type of the third transistor is identical to a channel type of the second transistor. ### Claim 4 (depends on 2) The gate driving circuit of claim 2, wherein the gate of the third transistor is electrically connected to one of the fourth node and the output end of the second output module, a channel type of the third transistor is identical to a channel type of the second transistor, and a voltage level of the low voltage signal is lower than a voltage level of the first low voltage signal. ### Claim 5 (depends on 4) The gate driving circuit of claim 4, wherein a difference between the voltage level of the first low voltage level signal and the voltage level of the low voltage signal is greater than or equal to 2V. ### Claim 6 (depends on 4) The gate driving circuit of claim 4, wherein the first inverting module comprises: a P-type fourth transistor, a first electrode of the fourth transistor is electrically connected to a second high voltage line, a second electrode of the fourth transistor is electrically connected to the fourth node, and a gate of the fourth transistor is electrically connected to the second node; and an N-type fifth transistor, a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor receives a second low voltage signal, and a gate of the fifth transistor is electrically connected to the second node; wherein a voltage level of the second low voltage signal is lower than a voltage level of the low voltage signal. ### Claim 7 (depends on 1) The gate driving circuit of claim 1, wherein the second transistor is a double-gate transistor, a first gate of the second transistor is electrically connected to the second node and a second gate of the second transistor; and the third transistor is a double-gate transistor, a first gate of the third transistor is electrically connected to the fourth node and a second gate of the third transistor. ### Claim 8 (depends on 2) The gate driving circuit of claim 2, wherein the gate of the third transistor is electrically connected to the first node of the shift register of the next stage, the low voltage signal is the first low voltage signal, and a channel type of the third transistor is different from a channel type of the second transistor; wherein the shift register further comprises: a sixth transistor, a first electrode of the sixth transistor is electrically connected to the second node, a second electrode of the sixth transistor is electrically connected to the gate of the first transistor, a gate of the sixth transistor is connected to the first clock signal, and a channel type of the sixth transistor is identical to a channel type of the first transistor. ### Claim 9 (depends on 8) The gate driving circuit of claim 8, wherein the voltage regulating module is configured to stabilize or reduce a low voltage level of the second node. ### Claim 10 (depends on 9) The gate driving circuit of claim 9, wherein the voltage regulating module is further configured to stabilize or reduce a voltage level of the gate of the second transistor during a positive pulse duration of the second gate driving signal. ### Claim 11 (depends on 1) The gate driving circuit of claim 1, wherein in a frame, after a pulse of each of the first gate driving signals and a pulse of each of the second gate driving signals in the gate driving circuit are completely outputted, the first clock signal is maintained at a low voltage level. ### Claim 12 (depends on 11) The gate driving circuit of claim 11, wherein the first output module outputs a received second clock signal as the first gate driving signal according to a voltage level of the third node; and after the pulse of each of the first gate driving signals and the pulse of each of the second gate driving signals in the gate driving circuit are completely outputted, the second clock signal is maintained at a low voltage level. ### Claim 13 A display panel, comprising: a pixel circuit, comprising: a writing transistor, configured to control an input of a data signal; and a compensation transistor, configured to control the data signal to be inputted to a gate of driving transistor; and a gate driving circuit comprising a plurality of shift registers, wherein at least one of the plurality of shift registers comprises: a cascade signal selection module, electrically connected between a first wiring and a first node; a pull-up control module, configured to conduct a voltage level of a first node to the second node in response to a first clock signal; a first filter module, electrically connected between the second node and a third node, wherein a control end of the first filter module receives a reset signal; a second filter module, electrically connected between the first filter module and the third node, wherein a control end of the second filter module receives a filter control signal; a first inverting module, connected between the second node and a fourth node; a first output module, configured to output a first gate driving signal according to a voltage level of the third node and a voltage level of the fourth node; a second output module, comprising a P-type first transistor and an N-type second transistor, wherein a first electrode of the first transistor is electrically connected to a first high voltage line, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor to output a second gate driving signal, a second electrode of the second transistor is receives a first low voltage signal, the second node is electrically connected to a gate of the first transistor and a gate of the second transistor; and a voltage regulating module, receiving a low voltage signal and connected to the gate of the second transistor, wherein a control end of the voltage regulating module is electrically connected to one of the fourth node, an output end of the second output module and the first node of the shift register of a next stage. ### Claim 14 (depends on 13) The display panel of claim 13, wherein the voltage regulating module comprises a third transistor, a first electrode of the third transistor is connected to the low voltage signal, a second electrode of the third transistor is electrically connected to the gate of the second transistor, a gate of the third transistor is electrically connected to one of the fourth node, the output end of the second output module and the first node of the shift register of the next stage. ### Claim 15 (depends on 14) The display panel of claim 14, wherein the gate of the third transistor is electrically connected to one of the fourth node and the output end of the second output module, the low voltage signal is the first low voltage signal, and a channel type of the third transistor is identical to a channel type of the second transistor. ### Claim 16 (depends on 14) The display panel of claim 14, wherein the gate of the third transistor is electrically connected to one of the fourth node and the output end of the second output module, a channel type of the third transistor is identical to a channel type of the second transistor, and a voltage level of the low voltage signal is lower than a voltage level of the first low voltage signal. ### Claim 17 (depends on 16) The display panel of claim 16, wherein a difference between the voltage level of the first low voltage level signal and the voltage level of the low voltage signal is greater than or equal to 2V. ### Claim 18 (depends on 16) The display panel of claim 16, wherein the first inverting module comprises: a P-type fourth transistor, a first electrode of the fourth transistor is electrically connected to a second high voltage line, a second electrode of the fourth transistor is electrically connected to the fourth node, and a gate of the fourth transistor is electrically connected to the second node; and an N-type fifth transistor, a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor receives a second low voltage signal, and a gate of the fifth transistor is electrically connected to the second node; wherein a voltage level of the second low voltage signal is lower than a voltage level of the low voltage signal. ### Claim 19 (depends on 13) The display panel of claim 13, wherein the second transistor is a double-gate transistor, a first gate of the second transistor is electrically connected to the second node and a second gate of the second transistor; and the third transistor is a double-gate transistor, a first gate of the third transistor is electrically connected to the fourth node and a second gate of the third transistor. ### Claim 20 (depends on 14) The display panel of claim 14, wherein the gate of the third transistor is electrically connected to the first node of the shift register of the next stage, the low voltage signal is the first low voltage signal, and a channel type of the third transistor is different from a channel type of the second transistor; wherein the shift register further comprises: a sixth transistor, a first electrode of the sixth transistor is electrically connected to the second node, a second electrode of the sixth transistor is electrically connected to the gate of the first transistor, a gate of the sixth transistor is connected to the first clock signal, and a channel type of the sixth transistor is identical to a channel type of the first transistor.