# US 12,183,262 B2 · Pixel compensation circuit, display panel, and pixel compensation method

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- Number: US 12,183,262 B2
- Document ID: US12183262B2
- Status: Granted
- Kind: B2
- Application number: 17/779,599
- Filed: 2022-05-18
- Published: 2024-06-13
- Granted: 2024-12-31
- Earliest claimed: 2022-04-18
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Xiang Yin
- Web page: https://patentgrep.com/patent/US12183262B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0242: Compensation of deficiencies in the appearance of colours
- G09G 2320/0626: for control of overall brightness
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure provides a pixel compensation circuit, a display panel, and a pixel compensation method. The pixel compensation circuit includes a first transistor, a driving transistor, a compensation transistor, a second transistor, a third transistor, a reset transistor, a storage capacitor, and a light-emitting device. The circuit of the present disclosure uses transistors having different types and complementary polarity, and the transistors are connected to a first scanning line and a second scanning line, respectively. Compared with a conventional pixel compensation circuit, the circuit of the present disclosure uses fewer scanning signal lines and simpler timing.

## Claims

### Claim 1

A pixel compensation circuit, comprising a first transistor, a driving transistor, a compensation transistor, a second transistor, a third transistor, a reset transistor, a storage capacitor, and a light-emitting device;
wherein a gate of the first transistor is electrically connected to a second scanning line, a source of the first transistor is electrically connected to a data line, and a drain of the first transistor is electrically connected to a first node, wherein the second scanning line is configured to provide a second scanning signal, and the data line is configured to provide a data signal;
wherein a gate of the driving transistor is electrically connected to a third node, a source of the driving transistor is electrically connected to a second node, and a drain of the driving transistor is electrically connected to the first node;
wherein a gate of the compensation transistor is electrically connected to a first scanning line, a source of the compensation transistor is electrically connected to the second node, and a drain of the compensation transistor is electrically connected to the third node, wherein the first scanning line is configured to provide a first scanning signal;
wherein a gate of the second transistor is electrically connected to the second scanning line, a source of the second transistor is electrically connected to the second node, and a drain of the second transistor is electrically connected to a positive electrode of a power supply;
wherein a gate of the third transistor is electrically connected to the first scanning line, a source of the third transistor is electrically connected to the first node, and a drain of the third transistor is electrically connected to the light-emitting device at a fourth node, wherein another end of the light-emitting device is electrically connected to a negative electrode of the power supply;
wherein a gate of the reset transistor is electrically connected to the first scanning line at a fifth node, the storage capacitor is electrically connected between a source of the reset transistor and the third node, a source of the reset transistor is electrically connected to the fourth node through a wire, and a drain of the reset transistor is electrically connected to a reset signal line; and
wherein the first transistor, the compensation transistor, and the reset transistor are unipolar transistors which have a type complementary to a type of the driving transistor, the second transistor, and the third transistor;
wherein the first scanning line and the second scanning line are combined to correspond to a reset phase, a data writing phase, and a light-emitting phase sequentially;
wherein in the reset phase, the first scanning line is at a low level and the second scanning line is at a high level; in the data writing phase, both the first scanning line and the second scanning line are at a low level; in the light-emitting phase, both the first scanning line and the second scanning line are at a high level.

### Claim 2 (depends on 1)

The pixel compensation circuit of claim 1, wherein the driving transistor, the second transistor, and the third transistor are N-channel thin film transistors.

### Claim 3 (depends on 2)

The pixel compensation circuit of claim 2, wherein each of the N-channel thin film transistors comprises an N-channel amorphous silicon transistor, an N-channel low temperature poly-silicon transistor, or an N-channel metal-oxide-semiconductor field-effect transistor.

### Claim 4 (depends on 1)

The pixel compensation circuit of claim 1, wherein the first transistor, the compensation transistor, and the reset transistor are P-channel thin film transistors.

### Claim 5 (depends on 4)

The pixel compensation circuit of claim 4, wherein each of the P-channel thin film transistors comprises a P-channel low temperature poly-silicon transistor, or a P-channel metal-oxide-semiconductor field-effect transistor.

### Claim 6 (depends on 1)

The pixel compensation circuit of claim 1, wherein in the reset phase, the compensation transistor, the second transistor, and the reset transistor are all in an on state; and the first transistor, the driving transistor, and the third transistor are all in an off state.

### Claim 7 (depends on 1)

The pixel compensation circuit of claim 1, wherein in the data writing phase, the first transistor, the compensation transistor, and the reset transistor are all in an on state; and the driving transistor, the second transistor, and the third transistor are all in an off state.

### Claim 8 (depends on 1)

The pixel compensation circuit of claim 1, wherein in the light-emitting phase, the second transistor and the third transistor are both in an on state; and the first transistor, the compensation transistor, and the reset transistor are all in an off state.

### Claim 9 (depends on 1)

The pixel compensation circuit of claim 1, wherein the first transistor is configured as a control switching transistor to control a data signal to write into the pixel compensation circuit.

### Claim 10 (depends on 1)

The pixel compensation circuit of claim 1, wherein the driving transistor is configured to drive the light-emitting device to emit a light.

### Claim 11 (depends on 1)

The pixel compensation circuit of claim 1, wherein the compensation transistor is configured to compensate a threshold voltage in the driving transistor.

### Claim 12 (depends on 1)

The pixel compensation circuit of claim 1, wherein the second transistor and the third transistor are configured as control switching transistors to control the light-emitting device to emit a light.

### Claim 13 (depends on 1)

The pixel compensation circuit of claim 1, wherein the reset transistor is configured to control a reset of the pixel compensation circuit.

### Claim 14 (depends on 1)

The pixel compensation circuit of claim 1, wherein the second scanning line and the first scanning line are parallel to each other and transmit signals independently.

### Claim 15 (depends on 1)

A display panel, wherein the display panel comprises the pixel compensation circuit of claim 1.

### Claim 16 (depends on 1)

A pixel compensation method, wherein the pixel compensation method comprises:
providing the pixel compensation circuit of claim 1;
providing a low level from the first scanning line, and providing a high level from the second scanning line, when entering a reset phase; wherein the compensation transistor, the second transistor, and the reset transistor all in an on state; the first transistor, the driving transistor, and the third transistor all in an off state; a positive power supply voltage is written to the second node and the third node; and a reset voltage is written to the fourth node;
providing a low level from the first scanning line and the second scanning line, when entering a data writing phase; wherein the first transistor, the compensation transistor, and the reset transistor are all in an on state; the driving transistor, the second transistor, and the third transistor are all in an off state; a data signal is written to the first node, and a voltage of the third node changes to a first voltage V1; the first voltage V1 satisfies: V1=Data+Vth, wherein Data is a data signal input from a data line, and Vth is a threshold voltage of the driving transistor; and
providing a high level from the first scanning line and the second scanning line, when entering a light-emitting phase; wherein the second transistor and the third transistor are both in an on state; the first transistor, the compensation transistor, and the reset transistor are all in an off state; the first voltage V1 of the third node is consumed; the first voltage V1 comprises the threshold voltage of the driving transistor, and the light-emitting device emits a light.