# US 12,183,258 B2 · Display device and method of driving display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,258 B2 - Document ID: US12183258B2 - Status: Granted - Kind: B2 - Application number: 17/869,200 - Filed: 2022-07-20 - Published: 2023-05-04 - Granted: 2024-12-31 - Earliest claimed: 2021-11-01 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Subin Kim; Se-Byung Chae; Hyunchang Kim - Web page: https://patentgrep.com/patent/US12183258B2 ## CPC - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3275: Details of drivers for data electrodes - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/30: using electroluminescent panels - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3225: using an active matrix - G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor} - G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)} - G09G 5/12: Synchronisation between the display unit and other units, e.g. other display units, video-disc players - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/021: Power management, e.g. power saving - G09G 2330/022: in absence of operation, e.g. no data being entered during a predetermined time - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state. ## Claims ### Claim 1 A display device comprising: a display panel displaying an image; a controller receiving an image signal and an external synchronization signal, determining whether the external synchronization signal is in a normal state, and generating a control signal; a driver generating a driving signal in response the control signal and providing the driving signal to the display panel, wherein the controller comprises: a synchronization signal generator generating an internal synchronization signal based on a reference clock signal; a corrector correcting the internal synchronization signal to generate a corrected synchronization signal when it is determined that the external synchronization signal is restored from an abnormal state to the normal state; and a control signal generator generating the control signal, and wherein the control signal generator receives the external synchronization signal, the internal synchronization signal, and the corrected synchronization signal, and generates the control signal based on the external synchronization signal when the external synchronization signal is synchronized with the corrected synchronization signal, generates the control signal based on the internal synchronization signal when the external synchronization signal is in the abnormal state, and generates the control signal based on the corrected synchronization signal when the external synchronization signal is not synchronized with the corrected synchronization signal. ### Claim 2 (depends on 1) The display device of claim 1, wherein the controller further includes a synchronization determination circuit determining whether the external synchronization signal is synchronized with the corrected synchronization signal. ### Claim 3 (depends on 2) The display device of claim 2, wherein the synchronization determination circuit generates a timing signal when the external synchronization signal is synchronized with the corrected synchronization signal, and wherein the control signal generator generates the control signal based on the external synchronization signal in response to the timing signal. ### Claim 4 (depends on 3) The display device of claim 3, wherein the synchronization determination circuit receives a preset allowable value and generates the timing signal when a difference between a start time of an active section of the external synchronization signal and a start time of an active section of the corrected synchronization signal is less than the preset allowable value. ### Claim 5 (depends on 3) The display device of claim 3, wherein the internal synchronization signal includes a vertical synchronization signal and a horizontal synchronization signal, wherein the corrected synchronization signal is a signal generated by correcting the horizontal synchronization signal, and wherein the controller further includes a state determination circuit generating a state signal for controlling an operation of the control signal generator based on the timing signal and the vertical synchronization signal. ### Claim 6 (depends on 5) The display device of claim 5, wherein the vertical synchronization signal includes information on a display section in which the image is displayed on the display panel and a blank section in which the image is not displayed on the display panel, and wherein the state determination circuit generates the state signal when the external synchronization signal is synchronized with the corrected synchronization signal and when the vertical synchronization signal is in the blank section. ### Claim 7 (depends on 1) The display device of claim 1, wherein one period of the corrected synchronization signal is different from one period of the internal synchronization signal. ### Claim 8 (depends on 7) The display device of claim 7, wherein one period of the corrected synchronization signal is greater than one period of the internal synchronization signal. ### Claim 9 (depends on 8) The display device of claim 8, wherein a first period of the corrected synchronization signal is less than a second period that is a subsequent period of the first period of the corrected synchronization signal. ### Claim 10 (depends on 1) The display device of claim 1, wherein the controller further includes an error determination circuit determining whether the external synchronization signal is in the abnormal state, wherein the error determination circuit provides an error detection signal to the control signal generator when it is determined that the external synchronization signal is in the abnormal state, and wherein the control signal generator generates the control signal based on the internal synchronization signal when the error detection signal is received. ### Claim 11 (depends on 10) The display device of claim 10, wherein the error determination circuit generates an error end signal when the external synchronization signal is restored from the abnormal state to the normal state and provides the error end signal to the corrector, and wherein the corrector generates the corrected synchronization signal by correcting the internal synchronization signal when the error end signal is received. ### Claim 12 (depends on 11) The display device of claim 11, wherein the error determination circuit generates the error detection signal when the external synchronization signal is in the abnormal state and a first period of the external synchronization signal is different from a second period of the external synchronization signal that is a subsequent to the first period. ### Claim 13 (depends on 12) The display device of claim 12, wherein the error determination circuit generates the error end signal when the external synchronization signal is restored from the abnormal state to the normal state and a third period of the external synchronization signal that is a subsequent to the second period of the external synchronization signal is the same as the first period. ### Claim 14 (depends on 1) The display device of claim 1, wherein the controller further includes an oscillator generating an oscillation signal having a predetermined frequency, and wherein the synchronization signal generator generates the internal synchronization signal based on the reference clock signal and the oscillation signal. ### Claim 15 (depends on 1) The display device of claim 1, wherein the driver includes: a source driver receiving the image data from the controller and providing a data signal for displaying the image on the display panel; and a gate driver providing a scan signal to the display panel, and wherein the control signal includes a first control signal for controlling the source driver and a second control signal for controlling the gate driver. ### Claim 16 A method of driving a display device including a display panel displaying an image, a controller receiving an image signal and generating a control signal, and a driver generating a driving signal in response the control signal and provide the driving signal to the display panel, the method comprising: determining whether an external synchronization signal provided to the controller is in a normal state; generating the control signal based on an internal synchronization signal generated based on a reference clock signal when it is determined that the external synchronization signal is in an abnormal state; generating a corrected synchronization signal by correcting the internal synchronization signal when the external synchronization signal is restored from the abnormal state to the normal state; determining whether the corrected synchronization signal is synchronized with the external synchronization signal; generating the control signal based on the corrected synchronization signal when the corrected synchronization signal is not synchronized with the external synchronization signal; and generating the control signal based on the external synchronization signal when the corrected synchronization signal is synchronized with the external synchronization signal. ### Claim 17 (depends on 16) The method of claim 16, further comprising: generating the control signal based on the external synchronization signal when it is determined that the external synchronization signal is in the normal state. ### Claim 18 (depends on 16) The method of claim 16, wherein a driving frame of the display panel includes a display section in which the image is displayed on the display panel and a blank section in which the image is not displayed on the display panel, the generating the control signal comprises: determining whether a timing at which the corrected synchronization signal is synchronized with the external synchronization signal is included in the blank section; and generating the control signal based on the external synchronization signal when the synchronized timing is included in the blank section. ### Claim 19 (depends on 18) The method of claim 18, wherein the generating the control signal further comprises: generating the control signal based on the external synchronization signal from a start time of the blank section when the synchronized timing is not included in the blank section.