# US 12,183,256 B2 · Gate driving unit, driving method, gate driving circuit, and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,256 B2 - Document ID: US12183256B2 - Status: Granted - Kind: B2 - Application number: 18/466,619 - Filed: 2023-09-13 - Published: 2023-12-28 - Granted: 2024-12-31 - Earliest claimed: 2020-09-02 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Guangliang Shang; Jie Zhang; Jiangnan Lu; Mei Li; Libin Liu - Web page: https://patentgrep.com/patent/US12183256B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3677: {suitable for active matrices only} - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit controls to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit controls to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal. ## Claims ### Claim 1 A gate driving unit, comprising a first input node control circuit and a charge pump circuit; wherein the first input node control circuit is electrically connected to a clock signal terminal, an input terminal and a first input node respectively, and is configured to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit is electrically connected to the first input node, an input clock signal terminal and a first node respectively, and is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal. ### Claim 2 (depends on 1) The gate driving unit according to claim 1, wherein the gate driving unit comprises an output circuit, the output circuit includes a first output transistor, a control electrode of the first output transistor is electrically connected to the first node, and a first electrode of the first output transistor is electrically connected to an output voltage terminal, and a second electrode of the first output transistor is electrically connected to a gate driving signal output terminal. ### Claim 3 (depends on 1) The gate driving unit according to claim 1, wherein the charge pump circuit includes an input energy storage sub-circuit, an on-off control sub-circuit and a first energy storage sub-circuit; a first end of the input energy storage sub-circuit is electrically connected to the input clock signal terminal, and a second end of the input energy storage sub-circuit is electrically connected to the first input node, the input energy storage sub-circuit is configured to store electrical energy and control a potential of the first input node according to a potential of the input clock signal; the on-off control sub-circuit is electrically connected to the first input node and the first node respectively, and is configured to connect to disconnect the first input node and the first node under the control of the potential of the first input node; the first energy storage sub-circuit is electrically connected to the first node and configured to store electrical energy and maintain the potential of the first node. ### Claim 4 (depends on 3) The gate driving unit according to claim 3, wherein the input energy storage sub-circuit includes an input capacitor, the first energy storage sub-circuit includes a first storage capacitor, and the on-off control sub-circuit includes an on-off control transistor; a first end of the input capacitor is electrically connected to the input clock signal terminal, and a second end of the input capacitor is electrically connected to the first input node; a first end of the first storage capacitor is electrically connected to the first node, and a second end of the first storage capacitor is electrically connected to a second voltage terminal; a control electrode of the on-off control transistor and a first electrode of the on-off control transistor are electrically connected to the first input node, and a second electrode of the on-off control transistor is electrically connected to the first node. ### Claim 5 (depends on 4) The gate driving unit according to claim 4, wherein a ratio between a capacitance value of the input capacitor and a capacitance value of the first storage capacitor is greater than or equal to 1 and less than or equal to 10. ### Claim 6 (depends on 1) The gate driving unit according to claim 1, wherein the charge pump circuit includes an input energy storage sub-circuit, an on-off control sub-circuit, a switch control sub-circuit and a first energy storage sub-circuit; a first end of the input energy storage sub-circuit is electrically connected to the first control node, and a second end of the input energy storage sub-circuit is electrically connected to the first input node, the input energy storage sub-circuit is configured to store electrical energy and control a potential of the first input node according to a potential of the first control node; the on-off control sub-circuit is electrically connected to the first input node and the first node respectively, and is configured to connect or disconnect the first input node and the first node under the control of the potential of the first input node; the first energy storage sub-circuit is electrically connected to the first node and is configured to store electrical energy and maintain the potential of the first node; the switch control sub-circuit is electrically connected to the first input node, the input clock signal terminal and the first control node, respectively, and is configured to connect to disconnect the input clock signal terminal and the first control node under the control of the potential of the first input node. ### Claim 7 (depends on 6) The gate driving unit according to claim 6, wherein the input energy storage sub-circuit includes an input capacitor, the first energy storage sub-circuit includes a first storage capacitor, and the on-off control sub-circuit includes an on-off control transistor; a first end of the input capacitor is electrically connected to the first control node, and a second end of the input capacitor is electrically connected to the first input node; a first end of the first storage capacitor is electrically connected to the first node, and a second end of the first storage capacitor is electrically connected to a second voltage terminal; a control electrode of the on-off control transistor and a first electrode of the on-off control transistor are electrically connected to the first input node, and a second electrode of the on-off control transistor is electrically connected to the first node. ### Claim 8 (depends on 6) The gate driving unit according to claim 6, wherein the switch control sub-circuit comprises a switch control transistor; a control electrode of the switch control transistor is electrically connected to the first input node, a first electrode of the switch control transistor is electrically connected to the input clock signal terminal, and a second electrode of the switch control transistor is electrically connected to the first control node. ### Claim 9 (depends on 1) The gate driving unit according to claim 1, wherein a polarity of the voltage signal of the first node is the same as a polarity of the voltage signal of the first input node. ### Claim 10 (depends on 1) The gate driving unit according to claim 1, wherein an absolute value of a voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node. ### Claim 11 (depends on 1) The gate driving unit according to claim 1, wherein the first input node control circuit comprises a first isolation node control sub-circuit and a first isolation sub-circuit; the first isolation node control sub-circuit is electrically connected to the clock signal terminal, the input terminal and a first isolation node respectively, and is configured to connect or disconnect the input terminal and the first isolation node under the control of the clock signal provided by the clock signal terminal; the first isolation sub-circuit is electrically connected to a second voltage terminal, the first isolation node and the first input node respectively, and is configured to connect the first isolation node and the first input node under the control of a second voltage signal provided by the second voltage terminal. ### Claim 12 (depends on 11) The gate driving unit according to claim 11, wherein the clock signal terminal includes a first clock signal terminal and a second clock signal terminal; the first isolation node control sub-circuit includes a first control transistor and a second control transistor; a control electrode of the first control transistor is electrically connected to the second clock signal terminal, a first electrode of the first control transistor is electrically connected to the input terminal, and a control electrode of the second control transistor is electrically connected to the first clock signal terminal, a first electrode of the second control transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the second control transistor is electrically connected to the first isolation node; or the clock signal terminal includes the second clock signal terminal, and the first isolation node control sub-circuit includes the first control transistor; the control electrode of the first control transistor is electrically connected to the second clock signal terminal, the first electrode of the first control transistor is electrically connected to the input terminal, and the second electrode of the first control transistor is electrically connected to the first isolation node; or the clock signal terminal includes the first clock signal terminal, and the first isolation node control sub-circuit includes the second control transistor; the control electrode of the second control transistor is connected to the first clock signal terminal, the first electrode of the second control transistor is electrically connected to the input terminal, and the second electrode of the second control transistor is electrically connected to the first isolation node. ### Claim 13 (depends on 11) The gate driving unit according to claim 11, wherein the first isolation sub-circuit comprises a first isolation transistor; a control electrode of the first isolation transistor is electrically connected to the second voltage terminal, a first electrode of the first isolation transistor is electrically connected to the first isolation node, and a second electrode of the first isolation transistor is electrically connected to the first input node. ### Claim 14 (depends on 1) The gate driving unit according to claim 1, further comprising a first node control circuit; wherein the first node control circuit is electrically connected to a second input node, a third voltage terminal and the first node, respectively, and is configured to write a third voltage signal inputted by the third voltage terminal into the first node under the control of a potential of the second input node. ### Claim 15 (depends on 14) The gate driving unit according to claim 14, wherein the first node control circuit comprises a first node control transistor; a control electrode of the first node control transistor is electrically connected to the second input node, a first electrode of the first node control transistor is electrically connected to the third voltage terminal, and a second electrode of the first node control transistor is electrically connected to the first node. ### Claim 16 (depends on 1) The gate driving unit according to claim 1, further comprising a first energy storage circuit; wherein the first energy storage circuit is electrically connected to the second node and the second clock signal terminal respectively, and is configured to control a potential of the second node based on the second clock signal. ### Claim 17 (depends on 1) The gate driving unit according to claim 1, further comprising a gate driving signal output terminal and a first energy storage circuit; wherein the first energy storage circuit is electrically connected to a second node and the gate driving signal output terminal respectively, and is configured to control a potential of the second node according to a gate driving signal outputted by the gate driving signal output terminal. ### Claim 18 (depends on 1) The gate driving unit according to claim 1, further comprising an output circuit; the output circuit is respectively electrically connected to the first node, a second node, a gate driving signal output terminal, an output voltage terminal and a second clock signal output terminal, and is configured to write an output voltage signal into the gate driving signal output terminal under the control of the potential of the first node, and control to write a second clock signal into the gate driving signal output terminal under the control of a potential of the second node; the output voltage terminal is used for providing the output voltage signal. ### Claim 19 A gate driving circuit comprising a gate driving unit, wherein the gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is electrically connected to a clock signal terminal, an input terminal and a first input node respectively, and is configured to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit is electrically connected to the first input node, an input clock signal terminal and a first node respectively, and is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal. ### Claim 20 A display device comprising a gate driving circuit, wherein the gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is electrically connected to a clock signal terminal, an input terminal and a first input node respectively, and is configured to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit is electrically connected to the first input node, an input clock signal terminal and a first node respectively, and is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal.