# US 12,183,237 B2 · Shift-register unit circuit, gate-driving circuit, display apparatus, and driving method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,237 B2 - Document ID: US12183237B2 - Status: Granted - Kind: B2 - Application number: 18/452,552 - Filed: 2023-08-20 - Published: 2023-12-07 - Granted: 2024-12-31 - Earliest claimed: 2018-07-27 - Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Xuehuan Feng; Yongqian Li - Web page: https://patentgrep.com/patent/US12183237B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 3/3266: Details of drivers for scan electrodes - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point. ## Claims ### Claim 1 A shift-register unit circuit comprising: a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point; wherein the anti-leak sub-circuit comprises at least two serially connected anti-leak transistors; wherein the output sub-circuit comprises a first output transistor, a second output transistor, and a third output transistor; wherein a control terminal of the first output transistor is connected to the first node; a first terminal of the first output transistor is connected to a fourth clock-signal line; a second terminal of the first output transistor is connected to a first output terminal; a control terminal of the second output transistor is connected to the first node; a first terminal of the second output transistor is connected to a fifth clock-signal line; a second terminal of the second output transistor is connected to a second output terminal; a control terminal of the second output transistor is connected to the first node; a first terminal of the second output transistor is connected to a sixth clock-signal line; a second terminal of the second output transistor is connected to a third output terminal; and the fourth clock signal line, the fifth clock signal line, and the sixth clock signal line are three different clock signal lines. ### Claim 2 (depends on 1) The shift-register unit circuit of claim 1, wherein the second input sub-circuit comprises an isolation sub-circuit, wherein the isolation sub-circuit is set between the first node and the blank-control node. ### Claim 3 (depends on 2) The shift-register unit circuit of claim 2, wherein the anti-leak sub-circuit comprises a first anti-leak transistor connected to the isolation sub-circuit. ### Claim 4 (depends on 3) The shift-register unit circuit of claim 3, wherein a control terminal of the first anti-leak transistor is connected to a first clock-signal line, a first terminal of the first anti-leak transistor is directly connected to the first node, a second terminal of the first anti-leak transistor is directly connected to the anti-leak connection point. ### Claim 5 (depends on 1) The shift-register unit circuit of claim 1, wherein the anti-leak sub-circuit comprises a second anti-leak transistor and a third anti-leak transistor, the second anti-leak transistor and the third anti-leak transistor being serially connected. ### Claim 6 (depends on 5) The shift-register unit circuit of claim 5, wherein the second anti-leak transistor and the third anti-leak transistor are configured to provide a high voltage signal from a high-voltage-signal line to the anti-leak connection point under control of the first node. ### Claim 7 (depends on 5) The shift-register unit circuit of claim 5, wherein a first terminal of the second anti-leak transistor is connected to a high-voltage-signal line, a second terminal of the second anti-leak transistor is connected to a first terminal of the third anti-leak transistor, and a second terminal of the third anti-leak transistor is directly connected to a second terminal of the first anti-leak transistor. ### Claim 8 (depends on 1) The shift-register unit circuit of claim 1, further comprising a display-reset sub-circuit configured to reset the first node under control of a display-reset signal provided from a reset-signal line after outputting the display-output signal in the display period. ### Claim 9 (depends on 1) The shift-register unit circuit of claim 1, further comprising a display-reset transistor; wherein a control terminal of the display-reset transistor in an n-th stage is connected to an output terminal of an (n+3)-th stage; a first terminal of the display-reset transistor is connected to a first signal line; and a second terminal of the display-reset transistor is directly connected to the anti-leak sub-circuit. ### Claim 10 (depends on 9) The shift-register unit circuit of claim 9, wherein the anti-leak sub-circuit comprises a fourth anti-leak transistor; wherein a control terminal of the fourth anti-leak transistor and the control terminal of the display-reset transistor are connected to the output terminal of the (n+3)-th stage; a first terminal of the fourth anti-leak transistor is directly connected to the second terminal of the display-reset transistor; and a second terminal of the fourth anti-leak transistor is directly connected to the first node. ### Claim 11 (depends on 9) The shift-register unit circuit of claim 9, wherein the second terminal of the display-reset transistor is directly connected to a second terminal of a first anti-leak transistor. ### Claim 12 (depends on 1) The shift-register unit circuit of claim 1, wherein the second control sub-circuit comprises a first pull-down transistor; wherein a control terminal of the first pull-down transistor is connected to the second node; a first terminal of the first pull-down transistor is connected to a first signal line; and a second terminal of the first pull-down transistor is directly connected to the anti-leak sub-circuit. ### Claim 13 (depends on 12) The shift-register unit circuit of claim 12, wherein the anti-leak sub-circuit comprises a fifth anti-leak transistor; wherein a control terminal of the fifth anti-leak transistor and the control terminal of the first pull-down transistor are connected to the second node; a first terminal of the fifth anti-leak transistor is directly connected to the second terminal of the first pull-down transistor; and a second terminal of the fifth anti-leak transistor is directly connected to the first node. ### Claim 14 (depends on 12) The shift-register unit circuit of claim 12, wherein the second terminal of the first pull-down transistor is directly connected to a second terminal of a first anti-leak transistor. ### Claim 15 (depends on 1) The shift-register unit circuit of claim 1, wherein the first control sub-circuit comprises a first control transistor and a second control transistor, the first control transistor having a first terminal and a control terminal commonly connected to a first pull-down control-signal line, and a second terminal connected to the second node; the second control transistor having a first terminal connected to the second node, a control terminal connected to the first node, and a second terminal connected to a first signal line providing a turn-off voltage level. ### Claim 16 (depends on 1) The shift-register unit circuit of claim 1, wherein the second control sub-circuit comprises a first pull-down transistor and a second pull-down transistor, the first pull-down transistor having a first terminal connected to the first node, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level; the second pull-down transistor having a first terminal connected to the output terminal, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level. ### Claim 17 (depends on 1) A gate-driving circuit, comprising N stages of shift-register unit circuits cascaded in series, the N stages of shift-register unit circuits comprising the shift-register unit circuit of claim 1; wherein a display-input terminal of an i-th stage of shift-register unit circuit is connected to an output terminal of a j-th stage of shift-register unit circuit, wherein N is an integer greater than 2, 1