# US 12,183,234 B2 · Display panel and display device

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- Number: US 12,183,234 B2
- Document ID: US12183234B2
- Status: Granted
- Kind: B2
- Application number: 17/853,539
- Filed: 2022-06-29
- Published: 2023-07-06
- Granted: 2024-12-31
- Earliest claimed: 2021-12-31
- Assignees: Xiamen Tianma Display Technology Co., Ltd.
- Applicants: Xiamen Tianma Display Technology Co., Ltd.
- Inventors: Zhoulin Ke
- Web page: https://patentgrep.com/patent/US12183234B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- H10K 59/00: Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2310/061: for resetting or blanking
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display panel and a display device are provided. The display panel includes a first display area and a second display area; and the second display area includes a transmission area. The sum of the resistivities of a first reset signal line, a first initialization signal line and a first bias adjustment signal line located in the first display area may not be greater than the sum of the resistivities of the second reset signal line, the second initialization signal line and the second bias adjustment signal line located in the second display area such that at least one of the first reset signal line, the first initialization signal line and the first these signal lines with relatively high resistivity requirements is disposed arranged on the film layer with a low signal lines resistivity of the signal line.

## Claims

### Claim 1

A display panel, comprising:
a plurality of pixel circuits and corresponding light-emitting elements, wherein a pixel circuit includes a driving transistor, and the driving transistor is configured to provide a driving current for the light-emitting element;
a reset signal line, an initialization signal line and a bias adjustment signal line, wherein the reset signal line is configured to provide a reset signal to a gate of the driving transistor, the initialization signal line is configured to provide an initialization signal to the light-emitting element, and the bias adjustment signal line is configured to provide a bias adjustment signal for the driving transistor; and
a first display area and a second display area, wherein the second display area includes a transmission area, the first display area includes a first reset signal line, a first initialization signal line and a first bias adjustment signal line that are directly electronically connected to a first pixel circuit, and the second display area includes a second reset signal line, a second initialization signal line and a second bias adjustment signal line that are directly electronically connected to a second pixel circuit,
wherein:
a resistivity of the first reset signal line is ρ11, a resistivity of the first initialization signal line is ρ12, a resistivity of the first bias adjustment signal line is ρ13, a resistivity of the second reset signal line is ρ21, a resistivity of the second initialization signal line is ρ22, and a resistivity of the first bias adjustment signal line is ρ23; and
ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23,
and wherein:
the first reset signal line and the second reset signal line are disposed in different layers in a direction perpendicular to a surface of the display panel; and/or
the first initialization signal line and the second initialization signal line are disposed in different layers in the direction perpendicular to the surface of the display panel; and/or
the first bias adjustment signal line and the second bias adjustment signal line are disposed in different layers in the direction perpendicular to the surface of the display panel.

### Claim 2 (depends on 1)

The display panel according to claim 1, wherein:
ρ11>ρ12 and/or ρ11>ρ13; and
ρ21>ρ22 and/or ρ21>ρ23.

### Claim 3 (depends on 1)

The display panel according to claim 1, wherein:
(ρ23−ρ13)>(ρ22−ρ12) and/or (ρ23−ρ13)>(ρ21−ρ11).

### Claim 4 (depends on 1)

The display panel according to claim 1, wherein:
the pixel circuit includes a reset transistor, an initialization transistor and a bias adjustment transistor;
the reset transistor is connected between the reset signal line and the gate of the driving transistor;
the initialization transistor is connected between the initialization signal line and the light-emitting element; and
the bias adjustment transistor is connected between the bias adjustment signal line and a first terminal or a second terminal of the driving transistor.

### Claim 5 (depends on 1)

The display panel according to claim 1, wherein:
the pixel circuit includes a reset transistor, an initialization transistor and a compensation transistor;
the reset transistor is connected between the reset signal line and a first terminal or a second terminal of the driving transistor, and the compensation transistor is connected between the gate and a second terminal of the driving transistor; and
the initialization transistor is connected between the initialization signal line and the light-emitting element,
wherein an operation process of the pixel circuit includes a bias adjustment stage, and, in the bias adjustment stage, the reset transistor is multiplexed as a bias adjustment transistor, and the reset signal line is multiplexed as the bias adjustment signal line.

### Claim 6 (depends on 5)

The display panel according to claim 5, wherein:
ρ11-ρ13 and ρ21=ρ23.

### Claim 7 (depends on 1)

The display panel according to claim 1, wherein:
when being orthographically projected to a plane parallel to a surface of the display panel, a distance between the first reset signal line and the first initialization signal line is D11, a distance between the first initialization signal line and the first bias adjustment signal line is D12, and a distance between the first reset signal line and the first bias adjustment signal line is D13;
when being projected to a plane parallel to the surface of the display panel, a distance between the second reset signal line and the second initialization signal line is D21, a distance between the second initialization signal line and the second bias adjustment signal line is D22, and a distance between the second reset signal line and the second bias adjustment signal line is D23; and
D11>D21 and/or D12>D22 and/or D13>D23.

### Claim 8 (depends on 1)

The display panel according to claim 1, wherein:
in the direction perpendicular to the surface of the display panel, the second reset signal line and the second initialization signal line at least partially overlap; and/or
the second reset signal line and the second bias adjustment signal line at least partially overlap; and/or
the second initialization signal line and the second bias adjustment signal line at least partially overlap.

### Claim 9 (depends on 1)

The display panel according to claim 1, wherein:
at least two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line are disposed in a same layer; and
the second reset signal line, the second initialization signal line and the second bias adjustment signal line are all disposed in different layers.

### Claim 10 (depends on 9)

The display panel according to claim 9, wherein:
two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line are disposed in a first layer and other of the first reset signal line, the first initialization signal line and the first bias adjustment signal line is disposed in a second layer; and
a resistivity of the first layer is smaller than a resistivity of the second layer.

### Claim 11 (depends on 10)

The display panel according to claim 10, wherein:
the first initialization signal line and the first bias adjustment signal line are disposed in the first layer; and
the first reset signal line is disposed in the second layer.

### Claim 12 (depends on 10)

The display panel according to claim 10, wherein:
the second reset signal line is disposed in a third layer;
the second initialization signal line is disposed in a fourth layer; and
the second bias adjustment signal line is disposed in a fifth layer,
wherein a resistivity of the fourth layer is smaller than a resistivity of the fifth layer;
and/or the resistivity of the fifth layer is smaller than a resistivity of the third layer.

### Claim 13 (depends on 12)

The display panel according to claim 12, wherein:
the fourth layer and the first layer are a same layer; and
the third layer and the second layer are a same layer.

### Claim 14 (depends on 1)

The display panel according to claim 1, wherein:
a line width of the first reset signal line is W11;
a line width of the first initialization signal line is W12
a line width of the first bias adjustment signal line is W13;
a line width of the second reset signal line is W21;
a line width of the second initialization signal line is W22;
a line width of the second bias adjustment signal line is W23; and
W11+W12+W13>W21+W22+W23.

### Claim 15 (depends on 14)

The display panel according to claim 14, wherein:
(W11−W21)>(W13−W23)≥(W12−W22).

### Claim 16 (depends on 1)

The display panel according to claim 1, wherein:
the second display area includes a transition area;
the transition area includes a pixel circuit;
the pixel circuit is configured to provide signals for sub-pixels of the second display area; and
the second reset signal line, the second initialization signal line, and the second bias adjustment signal line are connected to the pixel circuit of the transition area.

### Claim 17 (depends on 16)

The display panel according to claim 16, wherein:
a line width of the first reset signal line is W11;
a line width of the first initialization signal line is W12;
a line width of the first bias adjustment signal line is W13;
a line width of the second reset signal line is W21;
a line width of the second initialization signal line is W22;
a line width of the second bias adjustment signal line is W23; and
(W11+W12+W13)<(W21+W22+W23).

### Claim 18 (depends on 17)

The display panel according to claim 17, wherein:
(W22−W12)>(W21−W11) and/or (W23−W13)>(W21−W11).

### Claim 19

A display device, comprising:
a display panel, including:
a plurality of pixel circuits and corresponding light-emitting elements, wherein a pixel circuit includes a driving transistor, and the driving transistor is configured to provide a driving current for the light-emitting element;
a reset signal line, an initialization signal line and a bias adjustment signal line, wherein the reset signal line is configured to provide a reset signal to a gate of the driving transistor, the initialization signal line is configured to provide an initialization signal to the light-emitting element, and the bias adjustment signal line is configured to provide a bias adjustment signal for the driving transistor; and
a first display area and a second display area, wherein the second display area includes a transmission area, the first display area includes a first reset signal line, a first initialization signal line and a first bias adjustment a signal line that are directly electronically connected to a first pixel circuit, and the second display area includes a second reset signal line, a second initialization signal line and a second bias adjustment signal line that are directly electronically connected to a second pixel circuit,
wherein:
a resistivity of the first reset signal line is ρ11, a resistivity of the first initialization signal line is ρ12, a resistivity of the first bias adjustment signal line is ρ13, a resistivity of the second reset signal line is ρ21, a resistivity of the second initialization signal line is ρ22, and a resistivity of the first bias adjustment signal line is ρ23;
ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23;
a functional device is correspondingly disposed in the transmission area; and
the functional device receives or reflects light through the transmission area,
and wherein:
the first reset signal line and the second reset signal line are disposed in different layers in a direction perpendicular to a surface of the display panel; and/or
the first initialization signal line and the second initialization signal line are disposed in different layers in the direction perpendicular to the surface of the display panel; and/or
the first bias adjustment signal line and the second bias adjustment signal line are disposed in different layers in the direction perpendicular to the surface of the display panel.