# US 12,182,666 B2 · Stabilizer instrument specification for stabilizer circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,666 B2 - Document ID: US12182666B2 - Status: Granted - Kind: B2 - Application number: 18/067,641 - Filed: 2022-12-16 - Published: 2024-05-16 - Granted: 2024-12-31 - Earliest claimed: 2022-11-09 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Vadym Kliuchnikov; Michael Edward Beverland; Adam Edward Paetznick - Web page: https://patentgrep.com/patent/US12182666B2 ## CPC - G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation - G06F 11/004: {Error avoidance (G06F11/07 and subgroups take precedence)} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/3688: {for test execution, e.g. scheduling of test suites} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena - G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers - G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computing system including a processor configured to receive a stabilizer circuit specification of a stabilizer circuit that includes one or more elementary operations. The elementary operations are each selected from the group consisting of an allocation of one or more qubits in a stabilizer state, an allocation of one or more random classical bits, a Clifford unitary, a Pauli unitary conditional on respective parities of measurement outcomes and/or respective parities of the random classical bits, a joint multi-qubit Pauli measurement, and a destructive one-qubit Pauli measurement. The processor is further configured to compute a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification. The standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, and a plurality of bit matrices. The processor is further configured to store the standardized stabilizer instrument specification in memory. ## Claims ### Claim 1 A computing system comprising: a processor configured to: receive a stabilizer circuit specification of a stabilizer circuit that includes one or more elementary operations, wherein the one or more elementary operations are each selected from the group consisting of: an allocation of one or more qubits in a stabilizer state; an allocation of one or more random classical bits; a Clifford unitary; a Pauli unitary conditional on one or more respective parities of one or more measurement outcomes and/or one or more respective parities of the one or more random classical bits; a joint multi-qubit Pauli measurement; and a destructive one-qubit Pauli measurement; compute a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification, wherein the standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, and a plurality of bit matrices; and store the standardized stabilizer instrument specification in memory. ### Claim 2 (depends on 1) The computing system of claim 1, wherein the plurality of bit matrices include a first bit matrix, a second bit matrix, and a third bit matrix. ### Claim 3 (depends on 1) The computing system of claim 1, wherein the processor is configured to compute the standardized stabilizer instrument specification at least in part by: computing a Choi state family of the stabilizer instrument; and computing the standardized stabilizer instrument specification based at least in part on the Choi state family. ### Claim 4 (depends on 3) The computing system of claim 3, wherein the processor is further configured to: compute a zero-input-qubit stabilizer circuit specification based at least in part on the stabilizer circuit specification; and compute the Choi state family as the Choi state family of the zero-input-qubit stabilizer circuit specification. ### Claim 5 (depends on 4) The computing system of claim 4, wherein the processor is configured to compute the zero-input-qubit stabilizer circuit specification at least in part by coupling each of one or more input qubits of the stabilizer circuit specification to a respective Bell pair. ### Claim 6 (depends on 3) The computing system of claim 3, wherein the Choi state family is parameterized at least in part by: a Choi state input-output Clifford unitary; and a Choi state bit matrix. ### Claim 7 (depends on 6) The computing system of claim 6, wherein, when computing the standardized stabilizer instrument specification based at least in part on the Choi state family, the processor is further configured to: compute an additional Clifford unitary and an invertible bit matrix at least in part by computing a partition of the Choi state input-output Clifford unitary, wherein the invertible bit matrix is a transformation matrix from the Choi state input-output Clifford unitary into the additional Clifford unitary; and compute the input Clifford unitary and the output Clifford unitary based at least in part on the additional Clifford unitary. ### Claim 8 (depends on 7) The computing system of claim 7, wherein, when computing the standardized stabilizer instrument specification based at least in part on the Choi state family, the processor is further configured to: compute a plurality of additional bit matrices based at least in part on the Choi state bit matrix, the additional Clifford unitary and an inversion of the invertible bit matrix; and compute the plurality of bit matrices based at least in part on the plurality of additional bit matrices. ### Claim 9 (depends on 8) The computing system of claim 8, wherein: the processor is further configured to compute a relabeling matrix that maps one or more stabilizer circuit qubit labels of the stabilizer circuit to one or more respective stabilizer instrument qubit labels of the stabilizer instrument; and the processor is further configured to compute the plurality of bit matrices based at least in part on the relabeling matrix. ### Claim 10 (depends on 1) The computing system of claim 1, wherein the processor is configured to compute the standardized stabilizer instrument specification at least in part by iteratively incorporating the elementary operations included in the stabilizer circuit specification into the standardized stabilizer instrument specification, starting from a zero-operation stabilizer instrument specification. ### Claim 11 A method for use with a computing system, the method comprising: receiving a stabilizer circuit specification of a stabilizer circuit that includes one or more elementary operations, wherein the one or more elementary operations are each selected from the group consisting of: an allocation of one or more qubits in a stabilizer state; an allocation of one or more random classical bits; a Clifford unitary; a Pauli unitary conditional on one or more respective parities of one or more measurement outcomes and/or one or more respective parities of the one or more random classical bits; a joint multi-qubit Pauli measurement; and a destructive one-qubit Pauli measurement; computing a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification, wherein the standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, and a plurality of bit matrices; and storing the standardized stabilizer instrument specification in memory. ### Claim 12 (depends on 11) The method of claim 11, wherein the plurality of bit matrices include a first bit matrix, a second bit matrix, and a third bit matrix. ### Claim 13 (depends on 11) The method of claim 11, wherein computing the standardized stabilizer instrument specification includes: computing a Choi state family of the stabilizer instrument; and computing the standardized stabilizer instrument specification based at least in part on the Choi state family. ### Claim 14 (depends on 13) The method of claim 13, wherein computing the standardized stabilizer instrument specification further includes: computing a zero-input-qubit stabilizer circuit specification based at least in part on the stabilizer circuit specification; and computing the Choi state family as the Choi state family of the zero-input-qubit stabilizer circuit specification. ### Claim 15 (depends on 14) The method of claim 14, wherein computing the zero-input-qubit stabilizer circuit specification includes coupling each of one or more input qubits of the stabilizer circuit specification to a respective Bell pair. ### Claim 16 (depends on 13) The method of claim 13, wherein the Choi state family is parameterized at least in part by: a Choi state input-output Clifford unitary; and a Choi state bit matrix. ### Claim 17 (depends on 16) The method of claim 16, further comprising, when computing the standardized stabilizer instrument specification based at least in part on the Choi state family: computing an additional Clifford unitary and an invertible bit matrix at least in part by computing a partition of the Choi state input-output Clifford unitary, wherein the invertible bit matrix is a transformation matrix from the Choi state input-output Clifford unitary into the additional Clifford unitary; and computing the input Clifford unitary and the output Clifford unitary based at least in part on the additional Clifford unitary. ### Claim 18 (depends on 17) The method of claim 17, further comprising, when computing the standardized stabilizer instrument specification based at least in part on the Choi state family: computing a plurality of additional bit matrices based at least in part on the Choi state bit matrix, the additional Clifford unitary and an inversion of the invertible bit matrix; and computing the plurality of bit matrices based at least in part on the plurality of additional bit matrices. ### Claim 19 (depends on 18) The method of claim 18, further comprising: computing a relabeling matrix that maps one or more stabilizer circuit qubit labels of the stabilizer circuit to one or more respective stabilizer instrument qubit labels of the stabilizer instrument; and computing the plurality of bit matrices based at least in part on the relabeling matrix. ### Claim 20 A computing system comprising: a processor configured to: receive a stabilizer circuit specification of a stabilizer circuit; compute a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification, wherein the standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, a first bit matrix, a second bit matrix, and a third bit matrix, wherein computing the standardized stabilizer instrument specification includes: computing a Choi state family of the stabilizer instrument; and computing the standardized stabilizer instrument specification based at least in part on the Choi state family; and store the standardized stabilizer instrument specification in memory.