# US 12,182,664 B2 · Quantum chip system, quantum computing processing system and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,664 B2 - Document ID: US12182664B2 - Status: Granted - Kind: B2 - Application number: 17/287,759 - Filed: 2020-07-17 - Published: 2022-09-29 - Granted: 2024-12-31 - Earliest claimed: 2019-10-29 - Assignees: Origin Quantum Computing Technology Co., Ltd. - Applicants: Origin Quantum Computing Technology Co., Ltd. - Inventors: Weicheng Kong; Yongjie Zhao - Web page: https://patentgrep.com/patent/US12182664B2 ## CPC - G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control - G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers - G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation - G06N 10/80: Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract Embodiments of the disclosure provide a quantum chip system, a quantum computing processing system and an electronic apparatus, wherein one quantum chip system includes at least one first qubit, each first qubit includes at least two control electrodes, and a first event register for controlling the control electrode, wherein each first event register is configured for storing a control signal of the control electrode, and each first qubit corresponds to at least two first event registers. ## Claims ### Claim 1 A quantum computing processing system, comprising: A) a quantum chip system that comprises at least one first qubit, each first qubit comprising at least two control electrodes; and a first event register for controlling the control electrode, wherein each first event register is configured for storing a control signal of the control electrode, and each first qubit corresponds to at least two first event registers; wherein at least one first event register is configured for applying a null waveform to at least one control electrode of at least one first qubit when a computing operation is executed by a first qubit, wherein the computing operation is executed without participation of a control electrode under control of the null waveform; and B) a decoding conversion apparatus that generates a quantum program to control operation of the quantum chip system, wherein the decoding conversion apparatus comprises: a device for obtaining input instructions of an input program; a device for converting at least one first input instruction among the input instructions into a first quantum instruction, wherein each first quantum instruction is configured for triggering waveforms of at least two logic gates that control qubits in the quantum chip system within a specific period of time; and a device for outputting a quantum program, wherein the quantum program corresponds to the input program and contains a first quantum instruction. ### Claim 2 (depends on 1) The quantum computing processing system of claim 1, wherein the null waveform corresponds to a compensation waveform of the control electrode under control of the null waveform. ### Claim 3 (depends on 1) The quantum computing processing system of claim 1, wherein the first qubit is a superconducting qubit, and the at least two control electrodes comprise a microwave pulse control electrode and a DC pulse control electrode. ### Claim 4 (depends on 1) The quantum computing processing system of claim 1, wherein the first event register comprises at least one second event register, each second event register is configured for controlling control electrodes of at least two first qubits. ### Claim 5 (depends on 4) The quantum computing processing system of claim 4, wherein each second event register is configured for controlling DC pulse control electrodes of at least two first qubits. ### Claim 6 (depends on 1) The quantum computing processing system of claim 1, wherein the decoding conversion apparatus further comprises: a device for converting at least one second input instruction among the input instructions into a second quantum instruction, wherein each second quantum instruction is configured for triggering a waveform of a single logic gate that controls qubits in the quantum chip system; and wherein the quantum program further comprises the second quantum instruction. ### Claim 7 (depends on 6) The quantum computing processing system of claim 6, wherein the first input instruction is a program instruction which is more complex than the second input instruction, wherein the decoding conversion apparatus further comprises: a device for determining whether the input instruction is a first input instruction or a second input instruction. ### Claim 8 (depends on 1) The quantum computing processing system of claim 1, wherein each first quantum instruction is configured for triggering waveforms that control all relevant qubits in the quantum chip system within a specific period of time. ### Claim 9 (depends on 1) The quantum computing processing system of claim 1, wherein the first quantum instruction does not contain operands corresponding to qubits. ### Claim 10 (depends on 1) The quantum computing processing system of claim 1, wherein the waveforms of the at least two logic gates comprise a waveform corresponding to a null operation. ### Claim 11 (depends on 1) An electronic apparatus, comprising the quantum computing processing system of claim 1.