# US 12,182,661 B2 · Computing platform with heterogenous quantum processors

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- Number: US 12,182,661 B2
- Document ID: US12182661B2
- Status: Granted
- Kind: B2
- Application number: 17/097,955
- Filed: 2020-11-13
- Published: 2021-09-02
- Granted: 2024-12-31
- Earliest claimed: 2018-05-18
- Assignees: Rigetti & Co, LLC
- Applicants: Rigetti & Co, LLC
- Inventors: Chad Tyler Rigetti; William J. Zeng; Blake Robert Johnson; Nikolas Anton Tezak
- Web page: https://patentgrep.com/patent/US12182661B2

## CPC

- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G06N 10/80: Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
- G06F 13/1663: {Access to shared memory}
- G06F 15/16: Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)}
- G06N 3/0455: Auto-encoder networks; Encoder-decoder networks
- G06N 5/01: Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers
- G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
- G06N 20/00: Machine learning
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06N 3/045: Combinations of networks
- G06N 3/047: Probabilistic or stochastic networks
- G06N 7/01: Probabilistic graphical models, e.g. probabilistic networks
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

## Claims

### Claim 1

A hybrid quantum-classical computing platform comprising:
a first quantum processor unit (QPU) comprising a first classical local memory;
a second QPU comprising a second classical local memory; and
a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU,
wherein the first classical local memory and the second classical local memory are connected to the shared classical memory for transferring data between the first QPU and the second QPU.

### Claim 2 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the first QPU has higher fidelity than the second QPU.

### Claim 3 (depends on 2)

The hybrid quantum-classical computing platform of claim 2, wherein the first QPU is above the fault tolerant threshold for quantum error correction and the second QPU is below the fault tolerant threshold for quantum error correction.

### Claim 4 (depends on 3)

The hybrid quantum-classical computing platform of claim 3, wherein the fault tolerant threshold for quantum error correction is one percent gate infidelity for the surface code.

### Claim 5 (depends on 3)

The hybrid quantum-classical computing platform of claim 3, wherein the fault tolerant threshold for quantum error correction is one percent error for the surface code.

### Claim 6 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the first QPU operates at a higher clock rate than the second QPU.

### Claim 7 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the first QPU operates at a higher logical clock rate than the second QPU.

### Claim 8 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the first QPU operates at a higher repetition rate than the second QPU.

### Claim 9 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the shared classical memory is configured to refresh with data from the first classical local memory and the second classical local memory.

### Claim 10 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the shared classical memory comprises a first shared classical local memory and a second shared classical local memory, the first shared classical local memory being connected to the second shared classical local memory for sharing data between the first QPU and the second QPU.

### Claim 11 (depends on 10)

The hybrid quantum-classical computing platform of claim 10, wherein the first shared classical local memory and the second shared classical local memory are configured to refresh with data from the first classical local memory and the second classical local memory, respectively.

### Claim 12 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, wherein the shared classical memory is partitioned into a first portion, a second portion and a shared portion, wherein the first portion is dedicated to the first QPU, the second portion is dedicated to the second QPU, and the shared portion coordinates the flow of data through the shared classical memory.

### Claim 13 (depends on 1)

The hybrid quantum-classical computing platform of claim 1, further comprising a quantum communication link between the first QPU and the second QPU for teleportation of quantum states.

### Claim 14 (depends on 1)

A method of operating the hybrid quantum-classical computing platform of claim 1, the method comprising:
collecting a first set of data from the first QPU in the first classical local memory;
transferring the first set of data from the first classical local memory to the shared classical memory; and
transferring the first set of data from the shared classical memory to the second classical local memory.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first set of data is calibration data for the second QPU.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first set of data is error syndrome data for the second QPU.

### Claim 17 (depends on 14)

The method of claim 14, wherein the first set of data is optimization data for a quantum approximate optimization algorithm (QAOA) iteration being run on the second QPU.

### Claim 18 (depends on 14)

The method of claim 14, wherein the first set of data is optimization data for a variational-quantum-eigensolver (VQE) algorithm iteration being run on the second QPU.

### Claim 19 (depends on 14)

The method of claim 14, wherein the first set of data is optimization data for a machine learning (ML) classification algorithm iteration being run on the second QPU.

### Claim 20 (depends on 14)

The method of claim 14, wherein the first set of data is a reduced data set derived from a classical data set autoencoded on the first QPU.

### Claim 21 (depends on 14)

The method of claim 14, wherein the first QPU operates at a higher clock rate than the second QPU.

### Claim 22 (depends on 14)

The method of claim 14, wherein the first QPU operates at a higher logical clock rate than the second QPU.

### Claim 23 (depends on 14)

The method of claim 14, wherein the first QPU operates at a higher repetition rate than the second QPU.

### Claim 24 (depends on 14)

The method of claim 14, wherein the second QPU has higher fidelity than the first QPU.