# US 12,182,618 B2 · System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,618 B2 - Document ID: US12182618B2 - Status: Granted - Kind: B2 - Application number: 18/322,636 - Filed: 2023-05-24 - Published: 2023-09-21 - Granted: 2024-12-31 - Earliest claimed: 2019-08-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Praveen Kumar Gupta; Avinash N. Ananthakrishnan; Eugene Gorbatov; Stephen H. Gunther - Web page: https://patentgrep.com/patent/US12182618B2 ## CPC - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU - G06F 1/3296: by lowering the supply or operating voltage - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 1/324: by lowering clock frequency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed. ## Claims ### Claim 1 A processor comprising: a first core having a first size and to operate at a first power consumption level; at least one second core having a second size and to operate at a second power consumption level, the first size greater than the second size and the first power consumption level greater than the second power consumption level; and a power controller coupled to the first core and the at least one second core, the power controller to: receive a power budget for the first core and the at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first operating point comprising a first operating frequency and a first operating voltage for the first core and a second operating point comprising a second operating frequency and a second operating voltage for the at least one second core based at least in part on the scaled power budget, the first operating voltage greater than the second operating voltage; cause a voltage regulator coupled to a power rail to provide the first operating voltage to the power rail, the power rail coupled to the first core and the at least one second core; and receive policy information and based at least in part on the policy information, cause a clock generation circuit to provide a third operating frequency to the at least one second core, cause the clock generation circuit coupled to the first core and the at least one second core to provide a clock signal at the first operating frequency to the first core and provide another clock signal at the third operating frequency to the at least one second core, the third operating frequency different and higher than the second operating frequency. ### Claim 2 (depends on 1) The processor of claim 1, wherein the power controller is to: determine a first efficiency value for the first core based at least in part on the first operating point and a second efficiency value for the at least one second core based at least in part on the second operating point; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value when the hardware state change exceeds a threshold, and otherwise to not report the hardware state change. ### Claim 3 (depends on 1) The processor of claim 1, wherein the power controller is to receive second policy information and based at least in part on the second policy information, to cause the clock generation circuit to provide the second operating frequency to the at least one second core, the third operating frequency comprising an opportunistic operating frequency, the second policy information to prevent the at least one second core from operation at the opportunistic operating frequency. ### Claim 4 (depends on 1) The processor of claim 1, wherein the power controller is to access a voltage-frequency table based on the first operating point to obtain a value of at least the first operating voltage. ### Claim 5 (depends on 1) The processor of claim 1, wherein the power controller is to report hardware state change information to an operating system scheduler, the hardware state change information comprising at least one of an efficiency value and a performance value for the first core and the at least one second core. ### Claim 6 (depends on 5) The processor of claim 5, wherein the power controller is to: determine the efficiency value for the first core based at least in part on the first operating point; and determine the efficiency value for the at least one second core based at least in part on the second operating point. ### Claim 7 (depends on 6) The processor of claim 6, wherein the power controller is to: access a lookup table with at least a portion of the first operating point to determine the efficiency value for the first core; and access the lookup table with at least a portion of the second operating point to determine the efficiency value for the at least one second core. ### Claim 8 A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising: obtaining a value of a first operating voltage for a first core of a processor including the first core and at least one second core, from a voltage-frequency table based on a first operating point determined for the first core; obtaining a value of a second operating voltage for the at least one second core, from the voltage-frequency table based on a second operating point determined for the at least one second core, the second operating voltage less than the first operating voltage; causing a voltage regulator coupled to a common power rail to provide the first operating voltage to the common power rail, the common power rail coupled to the first core and the at least one second core; and causing a clock generation circuit coupled to the first core and the at least one second core to: based at least in part on policy information, provide a clock signal at a second operating frequency to the at least one second core, the second operating frequency different and higher than an operating frequency of the second operating point; and concurrently provide another clock signal at the first operating frequency to the first core. ### Claim 9 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the method further comprises determining to cause the clock generation circuit to provide the clock signal at the second operating frequency based on the policy information to indicate that the at least one second core can operate at an opportunistic operating frequency. ### Claim 10 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the method further comprises: preventing the clock generation circuit from providing the clock signal at the second operating frequency based on second policy information to prevent the at least one second core from operating at an opportunistic operating frequency; and causing the clock generation circuit to provide the clock signal at the operating frequency of the second operating point to the at least one second core. ### Claim 11 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the method further comprises: accessing a first entry of the voltage-frequency table based on the first operating point to obtain the value of the first operating voltage for the first core; and accessing another entry of the voltage-frequency table based on the value of the first operating voltage to obtain the second operating frequency. ### Claim 12 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the method further comprises reporting hardware state change information to an operating system scheduler, the hardware state change information comprising at least one of an efficiency value and a performance value for the first core and the at least one second core. ### Claim 13 (depends on 12) The non-transitory machine-readable medium of claim 12, wherein the method further comprises: determining the efficiency value for the first core based at least in part on the first operating point determined for the first core; and determining the efficiency value for the at least one second core based at least in part on the second operating point determined for the at least one second core. ### Claim 14 (depends on 12) The non-transitory machine-readable medium of claim 12, wherein the method further comprises: determining the performance value for the first core based at least in part on the first operating point determined for the first core; and determining the performance value for the at least one second core based at least in part on the second operating point determined for the at least one second core. ### Claim 15 (depends on 14) The non-transitory machine readable medium of claim 14, wherein the method further comprises accessing a lookup table with at least a portion of the first operating point determined for at least one of the first core and the second operating point determined for the at least one second core to determine the efficiency value for the first core and the efficiency value for the at least one second core. ### Claim 16 A system comprising: a processor comprising: a first core having a first size and to operate at a first power consumption level; at least one second core having a second size and to operate at a second power consumption level, the first size greater than the second size and the first power consumption level greater than the second power consumption level; and a power controller including a resource allocation circuit to: receive a power budget for the first core and the at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first operating point comprising a first operating frequency and a first operating voltage for the first core and a second operating point comprising a second operating frequency and a second operating voltage for the at least one second core based at least in part on the scaled power budget, the first operating voltage greater than the second operating voltage; cause a voltage regulator coupled to a common power rail to provide the first operating voltage to the common power rail, the common power rail coupled to the first core and the at least one second core; and based at least in part on policy information, cause a clock generation circuit coupled to the first core and the at least one second core to provide a clock signal at the first operating frequency to the first core and provide another clock signal at a third operating frequency to the at least one second core, the third operating frequency different and higher than the second operating frequency; and a dynamic random access memory coupled to the processor. ### Claim 17 (depends on 16) The system of claim 16, wherein the power controller is to: determine a first efficiency value for the first core based at least in part on the first operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value when the hardware state change exceeds a threshold, and otherwise to not report the hardware state change. ### Claim 18 (depends on 16) The system of claim 16, wherein the power controller is to receive second policy information and based at least in part on the second policy information, to cause the clock generation circuit to provide the second operating frequency to the at least one second core, the third operating frequency comprising an opportunistic operating frequency, the second policy information to prevent the at least one second core from operation at the opportunistic operating frequency.