# US 12,182,615 B2 · Mechanism to handle breakpoints in a multi-element processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,615 B2 - Document ID: US12182615B2 - Status: Granted - Kind: B2 - Application number: 17/899,710 - Filed: 2022-08-31 - Published: 2024-02-29 - Granted: 2024-12-31 - Earliest claimed: 2022-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Bryan Hornung; David Patrick - Web page: https://patentgrep.com/patent/US12182615B2 ## CPC - G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)} - G06F 11/3636: {by tracing the execution of the program} - G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 11/3648: {using additional hardware} - G06F 11/3612: {by runtime analysis (performance monitoring G06F11/3466)} - G06F 11/3644: {by instrumenting at runtime} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Devices and techniques for handling breakpoints in a multi-element processor are described herein. A compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles. ## Claims ### Claim 1 A compute node comprising: a hybrid threading processor; and hybrid threading fabric, wherein the hybrid threading fabric comprises a plurality of memory-compute tiles, wherein each of the plurality of memory-compute tiles includes respective compute elements and storage elements used to execute a kernel, and a respective breakpoint controller configured to initiate a breakpoint for the plurality of memory-compute tiles. ### Claim 2 (depends on 1) The compute node of claim 1, wherein each respective breakpoint controller is configured to assert a breakpoint request signal to a central controller to initiate the breakpoint. ### Claim 3 (depends on 2) The compute node of claim 2, wherein the central controller is configured to assert a breakpoint stop signal to the plurality of memory-compute tiles in response to detecting the breakpoint request signal from one of the respective breakpoint controllers. ### Claim 4 (depends on 2) The compute node of claim 2, wherein each respective breakpoint controller is configured to set respective breakpoint state variables to indicate that the breakpoint request signal is asserted. ### Claim 5 (depends on 4) The compute node of claim 4, wherein each respective breakpoint controller is configured to deassert the breakpoint request signal in response to one of the respective breakpoint state variables being unset. ### Claim 6 (depends on 1) The compute node of claim 1, wherein each respective breakpoint controller is configured to set respective breakpoint state variables to indicate that a breakpoint stop signal is asserted, the breakpoint stop signal provided by a central controller that manages breakpoints across the plurality of memory-compute tiles. ### Claim 7 (depends on 6) The compute node of claim 6, wherein each respective breakpoint controller is configured to use no operation (NOP) instructions to cause the respective compute elements to pause execution of the kernel. ### Claim 8 (depends on 1) The compute node of claim 1, wherein the hybrid threading processor and the hybrid threading fabric are included in a memory device of the compute node. ### Claim 9 An apparatus comprising: dispatch interface circuitry configured to communicate with a plurality of memory-compute tiles, wherein each of the plurality of memory-compute tiles includes respective compute elements and storage elements used to execute a kernel, and a respective breakpoint controller to initiate a breakpoint among the plurality of memory-compute tiles; wherein the dispatch interface circuitry is configured to: detect a breakpoint request signal that is asserted by one of the plurality of memory-compute tiles; and assert a breakpoint stop signal to the plurality of memory-compute tiles in response to detecting the breakpoint request signal. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein each respective breakpoint controller of the plurality of memory-compute tiles is configured to set a respective breakpoint state variable to indicate that the breakpoint stop signal is asserted. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein each respective breakpoint controller of the plurality of memory-compute tiles is configured to use no operation (NOP) instructions to cause the plurality of memory-compute tiles to pause execution of the kernel. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein each respective breakpoint controller of the plurality of memory-compute tiles is configured to discontinue use of NOP instructions to cause the plurality of memory-compute tiles to continue execution of the kernel. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the dispatch interface circuitry is configured to: detect that the breakpoint request signal is deasserted by one of the plurality of memory-compute tiles; and deassert the breakpoint stop signal to the plurality of memory-compute tiles in response to detecting the breakpoint request signal. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein each respective breakpoint controller of the plurality of memory-compute tiles is configured to unset a respective breakpoint state variable to indicate that the breakpoint stop signal is deasserted. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the dispatch interface circuitry is integrated in a hybrid threading fabric. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the hybrid threading fabric is included in a memory device. ### Claim 17 A method comprising: detecting, at a central controller of a coarse-grained reconfigurable array (CGRA) processor, a breakpoint request signal that is asserted by one of a plurality of processing elements of the CGRA processor, wherein the central controller is configured to communicate with a plurality of processing elements, wherein each of the plurality of processing elements includes respective functional elements and storage elements used to execute a kernel, and a respective breakpoint controller to initiate a breakpoint for the plurality of processing elements; and asserting a breakpoint stop signal to the plurality of processing elements in response to detecting the breakpoint request signal. ### Claim 18 (depends on 17) The method of claim 17, wherein each respective breakpoint controller of the plurality of processing elements is configured to set a respective breakpoint state variable to indicate that the breakpoint stop signal is asserted. ### Claim 19 (depends on 18) The method of claim 18, wherein each respective breakpoint controller of the plurality of processing elements is configured to use NOP instructions to cause the plurality of processing elements to pause execution of the kernel. ### Claim 20 (depends on 17) The method of claim 17, comprising: detecting that the breakpoint request signal is deasserted by one of the plurality of processing elements; and deasserting the breakpoint stop signal to the plurality of processing elements in response to detecting the breakpoint request signal.