Interrupt cache configuration
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsPhilip Ng, Anil Kumar
Life of this patent
Estimating the term…
Abstract
An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.
Claims20
An apparatus comprising:
- a processing unit configured to execute a plurality of interrupt service routines;
- and
- an interrupt cache including:
- cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines;
- and
- a cache manager component configured to generate an interrupt message for transmission to the processing unit based on detecting whether an interrupt received from the interrupt source is a hit or a miss to the plurality of interrupts stored in the cache storage, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.
An interrupt cache comprising:
- cache storage configured to store a plurality of cache entries for a plurality of interrupts, the plurality of interrupts identifying a plurality of interrupt events configured for execution, respectively, by a plurality of interrupt service routines by a processing unit;
- and
- a cache manager component configured to generate an interrupt message including at least one interrupt event of the plurality of interrupt events from the cache storage for transmission to the processing unit based on detecting whether a received interrupt event is a hit or a miss to the plurality of interrupt events.
A method comprising:
- receiving an interrupt by an interrupt cache from an interrupt source, the interrupt corresponding to an interrupt event configured for execution by an interrupt service routine executed by a processing unit;
- generating an interrupt message by the interrupt cache for transmission to the processing unit, the interrupt message including at least one interrupt from the interrupt cache that is to be replaced in the interrupt cache by the received interrupt, the at least one interrupt selected based on whether the received interrupt is a hit or a miss to at least one of a plurality of interrupts stored in the interrupt cache;
- and
- storing the received interrupt in the interrupt cache.
Dependencies are inferred from the claim text.