# US 12,182,571 B2 · Systems, methods, and apparatuses for tile load, multiplication and accumulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,571 B2 - Document ID: US12182571B2 - Status: Granted - Kind: B2 - Application number: 18/100,194 - Filed: 2023-01-23 - Published: 2023-07-27 - Granted: 2024-12-31 - Earliest claimed: 2017-03-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert Valentine; Menachem Adelman; Milind B. Girkar; Zeev Sperber; Mark J. Charney; Bret L. Toll; Rinat Rappoport; Jesus Corbal; Stanislav Shwartsman; Dan Baum; Igor Yanover; Alexander F. Heinecke; Barukh Ziv; Elmoustapha Ould-Ahmed-Vall; Yuri Gebil; Raanan Sade - Web page: https://patentgrep.com/patent/US12182571B2 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 7/485: Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} - G06F 7/4876: {Multiplying} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 7/762: {having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks (G06F7/764 - G06F7/768 take precedence)} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30014: {with variable precision} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30038: {using a mask} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30109: {having multiple operands in a single register} - G06F 9/30112: {comprising data of variable length} - G06F 9/30134: {Register stacks; shift registers} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30149: {of variable length instructions} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/30196: {using decoder, e.g. decoder per instruction set, adaptable or programmable decoders} - G06F 9/3818: {Decoding for concurrent execution} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 12/0207: {with multidimensional access, e.g. row/column, matrix} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F 2212/454: Vector or matrix data - G06F 2212/455: Image or video data - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory. ## Claims ### Claim 1 An apparatus comprising: a memory interface; matrix processing circuitry coupled to a memory via the memory interface, the matrix processing circuitry to execute instructions to perform matrix multiplication operations with a first source matrix comprising a first plurality of data elements and a second source matrix comprising a second plurality of data elements, wherein the first source matrix comprises a first plurality of matrix tiles and the second source matrix comprises a second plurality of matrix tiles, each matrix tile in the first plurality of matrix tiles comprising a subset of non-overlapping data elements of the first plurality of data elements and each matrix tile in the second plurality of matrix tiles comprising a subset of non-overlapping data elements of the second plurality of data elements; and a first plurality of vector registers to store a first tile comprising a first subset of non-overlapping data elements of the first plurality of data elements, a second plurality of vector registers to store a second tile comprising a second subset of non-overlapping data elements of the second plurality of data elements, and a third plurality of vector registers to store a result matrix tile comprising a plurality of result data elements; the matrix processing circuitry to multiply each data element of the first subset of non-overlapping data elements with a corresponding data element of the second subset of non-overlapping data elements to generate a corresponding plurality of products, and to add one or more products of the corresponding plurality of products to a corresponding accumulation data element to generate a corresponding result data element of the plurality of result data elements of the result matrix tile, wherein tile usage of the matrix processing circuitry is to be configured by an execution of a configuration instruction prior to the matrix processing circuitry to multiply each data element of the first subset of non-overlapping data elements with a corresponding data element of the second subset of non-overlapping data elements to generate a corresponding plurality of products, and to add one or more products of the corresponding plurality of products to a corresponding accumulation data element to generate a corresponding result data element of the plurality of result data elements of the result matrix tile, wherein tile usage at least includes to configure the matrix processing circuitry to handle particular tile dimensions as determined from a configuration accessed by the execution of the configuration instruction. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the matrix processing circuitry is to execute one or more load instructions to load the first subset of non-overlapping data elements of the first plurality of data elements from memory into the first plurality of vector registers and to load the second subset of non-overlapping data elements of the second plurality of data elements from memory into the second plurality of vector registers. ### Claim 3 (depends on 2) The apparatus of claim 2 further comprising: decode circuitry to decode the one or more load instructions to load the first subset of non-overlapping data elements of the first plurality of data elements from memory into the first plurality of vector registers and to load the second subset of non-overlapping data elements of the second plurality of data elements from memory into the second plurality of vector registers, each load instruction including a first operand to specify a corresponding subset of the first or second plurality of vector registers. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the one or more load instructions are to load 64-bit data elements from memory locations generated using a base and an index into the first plurality of vector registers and the second plurality of vector registers. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the first subset of non-overlapping data elements of the first plurality of data elements are to be stored in the first plurality of vector registers in column-major order and the second subset of non-overlapping data elements of the second plurality of data elements are to be stored in the second plurality of vector registers in row-major order. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a first size and each data element of the result data elements comprises a second size which is at least twice the first size. ### Claim 7 (depends on 6) The apparatus of claim 6 wherein the first and second sizes are specified in at least one opcode executed by the matrix processing circuitry. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the size of each data element of the result data elements is a doubleword. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the size of each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a word. ### Claim 10 (depends on 9) The apparatus of claim 9 wherein each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a half-precision floating-point value. ### Claim 11 A system comprising: a memory interface; a plurality of cores coupled to the memory interface, one or more cores of the plurality of cores to execute program code to schedule matrix multiplication operations; matrix processing circuitry coupled to a memory via the memory interface, the matrix processing circuitry to execute instructions to perform the matrix multiplication operations with a first source matrix comprising a first plurality of data elements and a second source matrix comprising a second plurality of data elements, wherein the first source matrix comprises a first plurality of matrix tiles and the second source matrix comprises a second plurality of matrix tiles, each matrix tile in the first plurality of matrix tiles comprising a subset of non-overlapping data elements of the first plurality of data elements and each matrix tile in the second plurality of matrix tiles comprising a subset of non-overlapping data elements of the second plurality of data elements; and a first plurality of vector registers to store a first tile comprising a first subset of non-overlapping data elements of the first plurality of data elements, a second plurality of vector registers to store a second tile comprising a second subset of non-overlapping data elements of the second plurality of data elements, and a third plurality of vector registers to store a result matrix tile comprising a plurality of result data elements; the matrix processing circuitry to multiply each data element of the first subset of non-overlapping data elements with a corresponding data element of the second subset of non-overlapping data elements to generate a corresponding plurality of products, and to add one or more products of the corresponding plurality of products to a corresponding accumulation data element to generate a corresponding result data element of the plurality of result data elements of the result matrix tile, wherein tile usage of the matrix processing circuitry is to be configured by an execution of a configuration instruction prior to the matrix processing circuitry to multiply each data element of the first subset of non-overlapping data elements with a corresponding data element of the second subset of non-overlapping data elements to generate a corresponding plurality of products, and to add one or more products of the corresponding plurality of products to a corresponding accumulation data element to generate a corresponding result data element of the plurality of result data elements of the result matrix tile, wherein tile usage at least includes to configure the matrix processing circuitry to handle particular tile dimensions as determined from a configuration accessed by the execution of the configuration instruction. ### Claim 12 (depends on 11) The system of claim 11 wherein the matrix processing circuitry is to execute one or more load instructions to load the first subset of non-overlapping data elements of the first plurality of data elements from memory into the first plurality of vector registers and to load the second subset of non-overlapping data elements of the second plurality of data elements from memory into the second plurality of vector registers. ### Claim 13 (depends on 12) The system of claim 12 wherein the matrix processing circuitry comprises: decode circuitry to decode the one or more load instructions to load the first subset of non-overlapping data elements of the first plurality of data elements from memory into the first plurality of vector registers and to load the second subset of non-overlapping data elements of the second plurality of data elements from memory into the second plurality of vector registers, each load instruction including a first operand to specify a corresponding subset of the first or second plurality of vector registers. ### Claim 14 (depends on 11) The system of claim 11 wherein the first subset of non-overlapping data elements of the first plurality of data elements are to be stored in the first plurality of vector registers in column-major order and the second subset of non-overlapping data elements of the second plurality of data elements are to be stored in the second plurality of vector registers in row-major order. ### Claim 15 (depends on 11) The system of claim 11 wherein each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a first size and each data element of the result data elements comprises a second size which is at least twice the first size. ### Claim 16 (depends on 15) The system of claim 15 wherein the first and second sizes are specified in at least one opcode executed by the matrix processing circuitry. ### Claim 17 (depends on 16) The system of claim 16, wherein the size of each data element of the result data elements is a doubleword. ### Claim 18 (depends on 17) The system of claim 17, wherein the size of each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a word. ### Claim 19 (depends on 18) The system of claim 18 wherein each data element of the first subset of non-overlapping data elements and each data element of the second subset of non-overlapping data elements comprises a half-precision floating-point value. ### Claim 20 A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform a plurality of operations comprising: scheduling matrix multiplication operations on matrix processing circuitry, wherein tile usage of the matrix processing circuitry is to be configured prior to matrix multiplication operations, wherein tile usage at least includes to configure the matrix processing circuitry to handle particular tile dimensions as determined from a configuration accessed by the execution of a configuration instruction; executing instructions to perform matrix multiplication operations with a first source matrix comprising a first plurality of data elements and a second source matrix comprising a second plurality of data elements, wherein the first source matrix comprises a first plurality of matrix tiles and the second source matrix comprises a second plurality of matrix tiles, each matrix tile in the first plurality of matrix tiles comprising a subset of non-overlapping data elements of the first plurality of data elements and each matrix tile in the second plurality of matrix tiles comprising a subset of non-overlapping data elements of the second plurality of data elements; and storing a first tile comprising a first subset of non-overlapping data elements of the first plurality of data elements in a first plurality of vector registers; storing a second tile comprising a second subset of non-overlapping data elements of the second plurality of data elements in a second plurality of vector registers; multiplying each data element of the first subset of non-overlapping data elements with a corresponding data element of the second subset of non-overlapping data elements to generate a corresponding plurality of products; and adding one or more products of the corresponding plurality of products to a corresponding accumulation data element to generate a corresponding result data element of a plurality of result data elements of a result matrix tile.