# US 12,182,569 B2 · Graphics processor unit with opportunistic inter-path reconvergence

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- Number: US 12,182,569 B2
- Document ID: US12182569B2
- Status: Granted
- Kind: B2
- Application number: 18/217,062
- Filed: 2023-06-30
- Published: 2023-11-02
- Granted: 2024-12-31
- Earliest claimed: 2020-09-30
- Assignees: Purdue Research Foundation
- Applicants: Purdue Research Foundation
- Inventors: Milind Kulkarni; Jad Hbeika
- Web page: https://patentgrep.com/patent/US12182569B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/30018: {Bit or string instructions}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A graphics processing unit and methods for comping and executing instructions with opportunistic inter-path reconvergence are provided. An single instruction multiple thread (SIMT) stack of graphics processing unit may store data entries, each data entry comprising an operand mask. The operand mask may include bits corresponding to threads of a warp. The graphics processing unit core may access an instruction for an entry on the SIMT stack. Each of the threads may execute the instruction using either a first set of operands or a second set of operands depending on the corresponding bits of the operand mask.

## Claims

### Claim 1

A single instruction multiple thread (SIMT) core comprising:
a SIMT stack configured to store data entries, each data entry comprising an operand mask, the operand mask comprising bits corresponding to threads of a warp, respectively,
wherein the graphics processing unit core is configured to:
access an instruction for an entry on the SIMT stack;
execute the instruction with at least one of the threads of a warp,
wherein each of the at least one of the threads execute the instruction using either a first set of operands or a second set of operands depending on the corresponding bits of the operand mask.

### Claim 2 (depends on 1)

The SIMT core of claim 1 further comprising:
an immediate dominator (IDOM) mask register comprising bits corresponding to the threads of the warp, respectively, the bits indicative of a thread active state or a thread inactive state.

### Claim 3 (depends on 2)

The SIMT core of claim 2, wherein the instruction is executed only with the threads indicated as active by the bits of the IDOM mask register.

### Claim 4 (depends on 1)

The SIMT core of the claim 1, wherein the entry of the SIMT stack further comprises a block program counter indicative of the memory location of the instruction for the data entry, wherein the instruction is accessed based on the block program counter.

### Claim 5 (depends on 4)

The SIMT core of claim 4, the entry of the SIMT stack further comprising a reconvergence program counter, wherein the graphics processor core if further configured to:
pop the entry from the stack in response to a program counter of the SIMT core being equal or greater than the reconvergence program counter.