# US 12,182,568 B2 · Systems and methods for computing dot products of nibbles in two tile operands

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- Number: US 12,182,568 B2
- Document ID: US12182568B2
- Status: Granted
- Kind: B2
- Application number: 18/449,651
- Filed: 2023-08-14
- Published: 2023-11-30
- Granted: 2024-12-31
- Earliest claimed: 2017-12-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Raanan Sade; Simon Rubanovich; Amit Gradstein; Zeev Sperber; Alexander Heinecke; Robert Valentine; Mark J. Charney; Bret Toll; Jesus Corbal; Elmoustapha Ould-Ahmed-Vall
- Web page: https://patentgrep.com/patent/US12182568B2

## CPC

- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 9/30109: {having multiple operands in a single register}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/323: {for indirect branch instructions}
- G06F 9/3824: {Operand accessing}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

## Claims

### Claim 1

An apparatus comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers; and
a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores comprising circuitry to perform operations corresponding to an instruction, the instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned, the operations including to:
for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
for each of K 32-bit elements of the row m of the first matrix:
multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and
store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the operations further include to perform saturation to generate the 32-bit result data element.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein to perform the saturation comprises to perform signed saturation.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein K is 4.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein M is one of 2, 4, 8, and 16.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first matrix is to be stored in a plurality of registers of the processor, and wherein the second matrix is to be stored in a plurality of registers of the processor.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising an interconnect interface coupled to the processor.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a bus controller interface coupled to the processor.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the cores comprise graphics cores.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the cores comprise heterogeneous graphics cores.

### Claim 11 (depends on 1)

The apparatus of claim 1, further comprising an instruction converter to convert the instruction into one or more instructions of a different instruction set executable by the cores.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned.

### Claim 13

An apparatus comprising:
circuitry to receive an instruction, the instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned; and
execution circuitry to perform operations corresponding to the instruction, including to:
for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
for each of K 32-bit elements of the row m of the first matrix:
multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and
store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the operations further include to perform saturation to generate the 32-bit result data element, wherein the first matrix is to be stored in a plurality of registers, and wherein the second matrix is to be stored in a plurality of registers.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein K is 4, and wherein M is one of 2, 4, 8, and 16.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned.

### Claim 17 (depends on 13)

The apparatus of claim 13, wherein the circuitry to receive the instruction is to convert the instruction into one or more other instructions.

### Claim 18

An apparatus comprising:
an instruction converter to convert a first instruction into one or more other instructions, the first instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned; and
execution circuitry to perform operations corresponding to the first instruction, including to:
for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
for each of K 32-bit elements of the row m of the first matrix:
multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and
store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the first matrix is to be stored in a plurality of registers, and wherein the second matrix is to be stored in a plurality of registers.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein K is 4, and wherein M is one of 2, 4, 8, and 16, and wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the operations further include to perform saturation to generate the 32-bit result data element.