# US 12,182,489 B2 · Enforcing simulation-based physical design rules to optimize circuit layout

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- Number: US 12,182,489 B2
- Document ID: US12182489B2
- Status: Granted
- Kind: B2
- Application number: 16/852,640
- Filed: 2020-04-20
- Published: 2020-10-22
- Granted: 2024-12-31
- Earliest claimed: 2019-04-22
- Assignees: Cirrus Logic, Inc.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Michael R. Kobe; David Kostusiak; Christian Larsen
- Web page: https://patentgrep.com/patent/US12182489B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 2119/10: Noise analysis or noise optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for enforcing design rules in a circuit layout may include providing a circuit schematic for an integrated circuit to a circuit simulator, wherein the circuit layout is derived from a circuit schematic, using the circuit simulator to simulate the circuit schematic and generate simulated electrical parameters for the integrated circuit, and using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

## Claims

### Claim 1

A method for enforcing design rules in a circuit layout, comprising:
providing a circuit schematic for an integrated circuit to a circuit simulator;
using the circuit simulator to perform a single simulation of the circuit schematic and generate simulated electrical parameters for the integrated circuit;
generating circuit layout based on the circuit schematic and the simulated electrical parameters; and
performing physical verification of the circuit layout, using the simulated electrical parameters from the single simulation during physical verification to define physical design rules for the circuit layout and enforce the physical design rules in the circuit layout without further simulation of the circuit schematic.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
back annotating and recording the simulated electrical parameters to the circuit schematic; and
extracting the simulated electrical parameters from the circuit schematic for using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

### Claim 3 (depends on 1)

The method of claim 1, wherein the simulated electrical parameters comprise one of a simulated voltage characteristic and a simulated current characteristic for each of at least two nets of the integrated circuit.

### Claim 4 (depends on 3)

The method of claim 3, wherein enforcing the physical design rules comprises enforcing the physical design rules for each of the at least two nets relative to each of the other of the at least two nets.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
the physical design rules include a minimum spacing requirement between two nets based on voltage of the two nets; and
enforcing the minimum spacing requirement comprises defining the minimum spacing requirement based on a maximum difference between simulated voltages of the two nets as recorded in the simulated electrical parameters in the circuit schematic.

### Claim 6 (depends on 1)

The method of claim 1, further comprising generating a physical circuit layout based on the simulated electrical parameters.

### Claim 7

A computer program product for enforcing design rules in a circuit layout, the computer program product comprising a computer usable medium having computer readable code physically embodied therein, said computer program product further comprising computer readable program code for:
providing a circuit schematic for an integrated circuit to a circuit simulator;
using the circuit simulator to perform a single simulation of the circuit schematic and generate simulated electrical parameters for the integrated circuit;
generating circuit layout based on the circuit schematic and the simulated electrical parameters; and
performing physical verification of the circuit layout, using the simulated electrical parameters from the single simulation during physical verification to define physical design rules of the circuit layout and enforce the physical design rules in the circuit layout without further simulation of the circuit schematic.

### Claim 8 (depends on 7)

The computer program product of claim 7, wherein the computer readable program code is further configured to:
back annotate and record the simulated electrical parameters to the circuit schematic; and
extract the simulated electrical parameters from the circuit schematic for using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

### Claim 9 (depends on 7)

The computer program product of claim 7, wherein the simulated electrical parameters comprise one of a simulated voltage characteristic and a simulated current characteristic for each of at least two nets of the integrated circuit.

### Claim 10 (depends on 7)

The computer program product of claim 7, wherein enforcing the physical design rules comprises enforcing the physical design rules for each of the at least two nets relative to each of the other of the at least two nets.

### Claim 11 (depends on 10)

The computer program product of claim 10, wherein:
the physical design rules include a minimum spacing requirement between two nets based on voltage of the two nets; and
enforcing the minimum spacing requirement comprises defining the minimum spacing requirement based on a maximum difference between simulated voltages of the two nets as recorded in the simulated electrical parameters in the circuit schematic.

### Claim 12 (depends on 7)

The computer program product of claim 7, wherein the computer readable program code is further configured to generate a physical circuit layout based on the simulated electrical parameters.

### Claim 13

A system for enforcing design rules in a circuit layout, comprising:
a processor; and
a memory device coupled to the processor, wherein the memory device stores a plurality of instructions that when executed by the processor provides at least one software module that includes:
a circuit simulator configured to:
receive a circuit schematic for an integrated circuit to a circuit simulator; and
simulate the circuit schematic and generate simulated electrical parameters for the integrated circuit;
a layout module configured to generate circuit layout based on the circuit schematic and the simulated electrical parameters; and
a verification module configured to perform physical verification of the circuit layout, using the simulated electrical parameters during physical verification to define physical design rules for the circuit layout and enforce the physical design rules in the circuit layout without further simulation of the circuit schematic.

### Claim 14 (depends on 13)

The integrated circuit design system of claim 13, wherein:
the circuit simulator is further configured to back annotate and record the simulated electrical parameters to the circuit schematic; and
the verification module is further configured to extract the simulated electrical parameters from the circuit schematic for using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

### Claim 15 (depends on 13)

The integrated circuit design system of claim 13, wherein the simulated electrical parameters comprise one of a simulated voltage characteristic and a simulated current characteristic for each of at least two nets of the integrated circuit.

### Claim 16 (depends on 15)

The integrated circuit design system of claim 15, wherein enforcing the physical design rules comprises enforcing the physical design rules for each of the at least two nets relative to each of the other of the at least two nets.

### Claim 17 (depends on 16)

The integrated circuit design system of claim 16, wherein:
the physical design rules include a minimum spacing requirement between two nets based on voltage of the two nets; and
enforcing the minimum spacing requirement comprises defining the minimum spacing requirement based on a maximum difference between simulated voltages of the two nets as recorded in the simulated electrical parameters in the circuit schematic.

### Claim 18 (depends on 13)

The integrated circuit design system of claim 13, further comprising a layout generation module configured to generate a physical circuit layout based on the simulated electrical parameters.