# US 12,182,441 B2 · Allocation of host memory buffer for sustained sequential writes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,441 B2 - Document ID: US12182441B2 - Status: Granted - Kind: B2 - Application number: 17/737,830 - Filed: 2022-05-05 - Published: 2023-11-09 - Granted: 2024-12-31 - Earliest claimed: 2022-05-05 - Assignees: SanDisk Technologies LLC - Applicants: Western Digital Technologies, Inc. - Inventors: Sagar Uttarwar; Disha Gundecha - Web page: https://patentgrep.com/patent/US12182441B2 ## CPC - G06F 3/0656: {Data buffering arrangements} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/061: {Improving I/O performance} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0882: Page mode - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aspects of a storage device for providing superior sustained sequential write (SSW) performance are disclosed. A controller on the storage device allocates buffer space in the host memory buffers (HMBs) on the host device for storage of relocation data, i.e., data to be folded or compacted. The controller or a hardware element therein can therefore allocate local SRAM (including TRAM) for use in accommodating incoming host writes. The increased SRAM allocation of relocation data without an attendant increase in cost or size to the storage device enables the storage device to perform operations in parallel and substantially increase SSW performance metrics. ## Claims ### Claim 1 A data storage apparatus, comprising: a non-volatile memory including a memory location; and a controller coupled to the non-volatile memory and configured to: allocate one or more host memory buffers (HMBs) in a host device for storing relocation data; store the relocation data in the allocated one or more HMBs, wherein an amount of the relocation data stored in the one or more HMBs is an integer multiple of a width of a page or a meta-page including single-level cell (SLC) data in the non-volatile memory, and a capacity of a relocation (RLC) buffer allocated in the one or more HMBs for storage of the relocation data is based on the width of the page or the meta-page in the non-volatile memory; and write the relocation data from the RLC buffer in the allocated one or more HMBs to the memory location. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the relocation data is written during one or both of folding or compaction. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the controller is configured to receive an input/output (I/O) instruction from the host device, the I/O instruction being a write instruction, and the controller includes a hardware acceleration (HAWA) buffer configured to store host data associated with the write instruction in parallel with the storage or write of the relocation data. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is configured: to enter a sustained write mode upon receiving consecutive sequential input/output (I/O) commands; and to fold SLC data into multi-level cell (MLC) data using the relocation data stored in the one or more HMBs while in the sustained write mode. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising static random-access-memory (SRAM) included in the controller, the SRAM including an additional RLC buffer for writing of the relocation data from the one or more HMBs to the memory location. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein a sustained sequential write speed of the data storage apparatus is based on the capacity of the RLC buffer in the one or more HMBs and a hardware acceleration (HAWA) buffer capacity in the controller. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the memory location is a multi-level cell (MLC) storage location. ### Claim 8 A data storage device, comprising: non-volatile memory including a plurality of storage locations; and a controller coupled to the non-volatile memory and configured to: receive successive write instructions from a host device; allocate host memory buffers (HMBs) in the host device for relocation data; retrieve the relocation data from the non-volatile memory to be stored in the HMBs, wherein an amount of the relocation data to be stored in the HMBs is an integer multiple of a width of a page or a meta-page including single-level cell (SLC) data in the non-volatile memory, and a capacity of relocation (RLC) buffers allocated in the HMBs for storage of the relocation data is based on the width of the page or the meta-page in the non-volatile memory; and write the relocation data from the RLC buffers in the HMBs while processing one or more of the successive write instructions. ### Claim 9 (depends on 8) The device of claim 8, wherein the relocation data is written during folding or compaction. ### Claim 10 (depends on 8) The device of claim 8, wherein the plurality of storage locations includes a plurality of multi-level cell (MLC) storage locations and a corresponding plurality of sets of single-level cell (SLC) storage locations, and each of the corresponding plurality of sets of SLC storage locations equals a capacity of one of the plurality of MLC storage locations. ### Claim 11 (depends on 10) The device of claim 10, wherein the controller is further configured to store the relocation data in the HMBs, the relocation data being retrieved from one of the corresponding plurality of sets of then SLC storage locations and written during folding to one of the MLC storage locations during processing of the one or more of the successive write instructions. ### Claim 12 (depends on 10) The device of claim 10, wherein the MLC storage locations include one of triple-level-cell (TLC) storage locations or quadruple-level cell (QLC) storage locations. ### Claim 13 (depends on 8) The device of claim 8, wherein the controller is configured to: fold single-level cell (SLC) data into multi-level cell (MLC) data using the relocation data stored in the HMBs during a sustained write mode. ### Claim 14 (depends on 8) The device of claim 8, wherein the controller is further configured to set a value for a toggle mode for optimized sustained sequential write performance. ### Claim 15 (depends on 8) The device of claim 8, further comprising a hardware acceleration (HAWA) module configured to: retrieve data associated with the one or more of the successive write instructions from a random access memory (RAM) in the host device; transfer the retrieved data to a transfer random access memory (TRAM) in the controller for incoming host data accumulation; and send a notification to the controller identifying the data transfer. ### Claim 16 (depends on 15) The device of claim 15, wherein a sustained sequential write speed of the data storage device is based on the capacity of the RLC buffers including the relocation data and a capacity of buffers associated with the HAWA module. ### Claim 17 A data storage apparatus, comprising: a volatile memory; a non-volatile memory including a plurality of memory locations; and a controller coupled to the non-volatile memory and the volatile memory and configured to: receive a plurality of sequential write operations from a host device; execute one of the plurality of sequential write operations to store data in one of the memory locations; and allocate, during execution of the one of the sequential write operations, relocation data in a first capacity to the volatile memory and in a second capacity to a host memory buffer (HMB) in the host device, wherein an amount of the relocation data allocated to the HMB is an integer multiple of a width of a page or a meta-page including single-level cell (SLC) data in the non-volatile memory, and a capacity of a relocation (RLC) buffer allocated in the HMB for storage of the relocation data is based on the width of the page or the meta-page in the non-volatile memory.