# US 12,182,416 B2 · Memory device and memory system including the same

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- Number: US 12,182,416 B2
- Document ID: US12182416B2
- Status: Granted
- Kind: B2
- Application number: 17/885,822
- Filed: 2022-08-11
- Published: 2023-05-11
- Granted: 2024-12-31
- Earliest claimed: 2021-11-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jung Min You; Seong-Jin Cho
- Web page: https://patentgrep.com/patent/US12182416B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0673: {Single storage device}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 13/1636: {using refresh}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G06F 2212/70: Details relating to dynamic memory management
- G11C 11/40622: {Partial refresh of memory arrays}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.

## Claims

### Claim 1

A memory device, comprising:
a memory cell array including a plurality of memory cells; and
a control logic including a mode register, the control logic configured to:
perform a first refresh operation in response to a first refresh command,
generate an internal mode register write command in response to the first refresh command in a first mode,
in the first mode, write a bank address and a row address, on which the first refresh operation is performed, to the mode register in response to the internal mode register write command, and
perform a second refresh operation in response to a second refresh command in a second mode different from the first mode, wherein:
the internal mode register write command includes a first internal mode register write command and a second internal mode register write command,
the mode register includes a first mode register and a second mode register, and
the control logic is configured to write the bank address to the first mode register in response to the first internal mode register write command, and write the row address to the second mode register in response to the second internal mode register write command.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1, wherein the control logic is configured to generate the first internal mode register write command, and then generate the second internal mode register write command.

### Claim 3 (depends on 1)

The memory device as claimed in claim 1, wherein the control logic is configured to generate the second internal mode register write command and then generates the first internal mode register write command.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1, wherein the first mode register and the second mode register are consecutive.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1, wherein the control logic is configured to:
write mode information to the first mode register, and
operate in one of the first mode and the second mode according to the mode information.

### Claim 6 (depends on 1)

The memory device as claimed in claim 1, wherein:
the mode register further includes a third mode register, and
the control logic is configured to:
write mode information to the third mode register in response to the mode register write command, and
operate in one of the first mode and the second mode according to the mode information.

### Claim 7

A memory system, comprising:
a memory controller configured to generate a refresh command; and
a memory device which includes a memory cell array and a control logic, the memory cell array including a plurality of memory cells, the control logic including a mode register and configured to perform a refresh operation in response to the refresh command,
wherein the memory device is configured to:
store a bank address and a row address, on which the refresh operation is performed, in the mode register, and
output the bank address and the row address from the mode register to the memory controller outside the memory device in response to a mode register read command received from the memory controller,
wherein, in a first mode, the control logic is configured to store the bank address and the row address in the mode register in response to the refresh command,
wherein the mode register read command includes first and second mode register read commands, and
wherein the memory device is configured to output one of the bank address and the row address to the memory controller in response to the first mode register read command and output the other of the bank address and the row address to the memory controller in response to the second mode register read command.

### Claim 8 (depends on 7)

The memory system as claimed in claim 7, wherein:
the mode register includes a first mode register and a second mode register, and
the control logic is configured to store the bank address in the first mode register and store the row address in the second mode register.

### Claim 9 (depends on 8)

The memory system as claimed in claim 8, wherein the first mode register and the second mode register are consecutive.

### Claim 10 (depends on 7)

The memory system as claimed in claim 7, wherein the control logic is configured to:
write mode information to the mode register in response to a mode register write command from the memory controller, and
operate in one of the first mode and a second mode different from the first mode according to the mode information.

### Claim 11 (depends on 10)

The memory system as claimed in claim 10, wherein:
the mode register includes a first mode register and a second mode register, and
the control logic is configured to store the mode information and the bank address in the first mode register, and store the row address in the second mode register.

### Claim 12 (depends on 10)

The memory system as claimed in claim 10, wherein:
the mode register includes a first mode register, a second mode register, and a third mode register, and
the control logic is configured to store the mode information in the first mode register, store the bank address in the second mode register, and store the row address in the third mode register.

### Claim 13 (depends on 7)

The memory system as claimed in claim 7, wherein:
the memory controller includes a register clock driver, and
the register clock driver is configured to store the bank address and the row address.

### Claim 14

A memory device, comprising:
a memory cell array including a plurality of memory cells; and
a control logic including a mode register, wherein:
the control logic is configured to:
receive a first refresh command and a second refresh command after receiving the first refresh command,
perform a first refresh operation in response to the first refresh command, and a second refresh operation in response to the second refresh command,
store a first bank address and a first row address, on which the first refresh operation is performed, in the mode register in response to the first refresh command,
store a second bank address and a second row address, on which the second refresh operation is performed, in the mode register in response to the second refresh command,
output the first bank address and the first row address from the mode register to an outside of the memory device in response to a first mode register read command from the outside of the memory device in at least a portion of a period in which the first refresh operation is performed by receiving the first refresh command, and
output a second bank address and a second row address to the outside of the memory device from the mode register in response to a second mode register read command from the outside of the memory device in at least a portion of a period in which the second refresh operation is performed by receiving the second refresh command,
the second bank address is different from the first bank address, and
the second row address is different from the first row address.