# US 12,182,413 B2 · Area-optimized row hammer mitigation

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- Number: US 12,182,413 B2
- Document ID: US12182413B2
- Status: Granted
- Kind: B2
- Application number: 17/897,813
- Filed: 2022-08-29
- Published: 2023-07-27
- Granted: 2024-12-31
- Earliest claimed: 2022-01-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sujeet Ayyapureddi; Yang Lu; Edmund Gieske; Cagdas Dirik; Ameen D. Akel; Elliott C. Cooper-Balis; Amitava Majumdar; Danilo Caraccio; Robert M. Walker
- Web page: https://patentgrep.com/patent/US12182413B2

## CPC

- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0673: {Single storage device}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 15/04: using semiconductor elements
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

## Claims

### Claim 1

An apparatus configured to mitigate a row hammer event, comprising:
a memory media device;
a content addressable memory (CAM) configured to store a plurality of counters, each counter comprising a row identifier and a count, wherein a total number of counters is less than a total number of rows monitorable in the memory media device; and
circuitry configured to perform operations comprising:
determining whether a row identifier of a row access request is stored in the CAM;
when the determining determines that the row identifier is stored in the CAM, updating the count of a counter corresponding to the row identifier in the plurality of counters, and if the count exceeds a predetermined threshold, triggering a response to an error in the memory media device;
when the determining determines that the row identifier is not stored in the CAM, updating a counter of the plurality of counters to include the row identifier;
wherein updating the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the CAM among all rows of the CAM excluding rows in which a sticky bit is set;
inserting the row identifier in the CAM in a row that corresponds to the identified minimum count; and
incrementing the count in the row that corresponds to the identified minimum count.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a memory error detector arranged in the memory media device.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising an interface to a memory error detector in a memory controller.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the CAM and the circuitry are configured to perform deterministic detection of row hammer errors in the memory media device without any false negative detections by using ping-pong reset of the plurality of counters.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the circuitry is configured to limit a maximum number of false positive detections based at least in part on a maximum number of counters stored in the CAM.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein each counter further comprises a sticky bit, and wherein the circuitry is further configured to, if the count exceeds the predetermined threshold, further set the count to an initial value and set the sticky bit of the counter. the row that corresponds to the identified minimum count.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising circuitry configured to monitor all rows of one bank of a plurality of banks of the memory media device.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising circuitry configured to monitor all rows of each bank of a plurality of banks in a channel of the memory media device.

### Claim 9 (depends on 1)

The apparatus of claim 1, further comprising circuitry configured to monitor all rows of a plurality of banks.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein determining whether a row identifier of the row access request is stored in the CAM comprises a parallel lookup of all rows stored in the CAM to determine whether a matching entry for the row identifier of the row access request is present.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein updating the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the CAM and inserting the row identifier in the CAM in a location that corresponds to the identified minimum count; and
incrementing the identified minimum count associated with the inserted row identifier.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the memory media device is dynamic random access memory (DRAM), and wherein a respective bank corresponds to a plurality of rows in the DRAM.

### Claim 13 (depends on 1)

The apparatus of claim 1, further comprising circuitry configured to clear the plurality of counters in each refresh interval of the memory media device.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the response comprises a digital refresh management (DRFM) command to refresh one or more physically adjacent rows of a row corresponding to the row identifier.

### Claim 15

A method performed by an apparatus configured to mitigate a row hammer event, comprising a content-addressable memory (CAM) and a memory media device, the method comprising:
determining whether a row identifier of a row access request is present in a plurality of counters stored in the CAM, wherein each counter of a plurality of counters comprises a row identifier and a count, and a total number of counters in the plurality of counters is less than a total number of rows monitorable in the memory media device;
determining whether a row identifier of a row access request is stored in the CAM;
when the determining determines that the row identifier is stored in the CAM, updating the count of a counter corresponding to the row identifier in the plurality of counters, and if the count exceeds a predetermined threshold, triggering a response to an error in the memory media device;
when the determining determines that the row identifier is not stored in the CAM, updating a counter of the plurality of counters to include the row identifier;
wherein updating the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the CAM among all rows of the CAM excluding rows in which a sticky bit is set;
inserting the row identifier in the CAM in a row that corresponds to the identified minimum count; and
incrementing the count in the row that corresponds to the identified minimum count.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the method further comprises performing deterministic detection of row hammer errors in the memory media device without any false negative detections by using ping-pong reset of the plurality of counters.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the method further comprises limiting a maximum number of false positive detections based at least in part on a maximum number of counters stored in the CAM.

### Claim 18

A memory controller comprising:
a first interface to a host system;
a second interface coupled to a memory media device, wherein the second interface comprises a plurality of physical interfaces to the memory media device and each of the physical interfaces corresponds to a respective channel having a plurality of banks;
at least one memory error detector comprising:
a content addressable memory (CAM) storing a plurality of counters, each counter comprising a row identifier and a count, and a total number of counters stored in the CAM is less than a total number of rows monitorable in the memory media device; and
circuitry configured to perform operations to mitigate a row hammer event, comprising:
determining whether a row identifier of a row access request is stored in the CAM;
when the determining determines that the row identifier is stored in the CAM, updating the count of a counter corresponding to the row identifier in the plurality of counters, and if the count exceeds a predetermined threshold, triggering a response to an error in the memory media device;
when the determining determines that the row identifier is not stored in the CAM, updating a counter of the plurality of counters to include the row identifier;
wherein updating the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the CAM among all rows of the CAM excluding rows in which a sticky bit is set;
inserting the row identifier in the CAM in a row that corresponds to the identified minimum count; and
incrementing the count in the row that corresponds to the identified minimum count.

### Claim 19 (depends on 18)

The memory controller according to claim 18, wherein the CAM and the circuitry are arranged to perform deterministic detection of row hammer errors in the memory media device without any false negative detections by using ping-pong reset of the plurality of counters.