# US 12,182,399 B2 · Memory system and control method based on quad-serial peripheral interface (SPI) controller with external memory system based on SPI standard > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,399 B2 - Document ID: US12182399B2 - Status: Granted - Kind: B2 - Application number: 17/897,064 - Filed: 2022-08-26 - Published: 2023-08-17 - Granted: 2024-12-31 - Earliest claimed: 2022-02-15 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Kiyotaka Hayashi; Kyoko Shoji - Web page: https://patentgrep.com/patent/US12182399B2 ## CPC - G06F 3/0605: {by facilitating the interaction with a user or administrator} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/4291: {using a clocked protocol} - G06F 2213/0002: Serial port, e.g. RS232C - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A memory system includes a nonvolatile memory and a serial peripheral interface (SPI) controller communicable with an external controller external to the memory system in accordance with an SPI standard, a first terminal through which the SPI controller receives a command, and a second terminal. The SPI controller is configured to operate in one of a plurality of operational modes in accordance with the command received through the first terminal. The operational modes include a first mode in which a signal received through the second terminal is used as a control signal to perform a predetermined function and a second mode in which the signal is not used as the control signal to perform the predetermined function. ## Claims ### Claim 1 A memory system comprising: a nonvolatile memory; a serial peripheral interface (SPI) controller communicable with an external controller external to the memory system in accordance with an SPI standard; a first terminal through which the SPI controller receives a command; and a second terminal, wherein the SPI controller is configured to operate in one of a plurality of operational modes in accordance with the command received through the first terminal, the operational modes including a first mode in which a signal received through the second terminal is used by the SPI controller as a control signal to perform a predetermined function and a second mode in which the signal received through the second terminal is not used by the SPI controller as the control signal to perform the predetermined function, and in the second mode, a second signal of a predetermined length received through the first terminal following the command is used by the SPI controller as an address of the nonvolatile memory to be accessed, and the SPI controller is configured to perform an operation to disable the predetermined function during reception of the second signal used as the address through the first terminal. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the predetermined function includes a function of pausing communication through the first terminal. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein in the first mode, the first terminal is used for data input, and not for data output, and in the second mode, each of the first and second terminals is used for data input and data output. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein, in the second mode, a third signal received through the first terminal following the address is used by the SPI controller as data to be written into the nonvolatile memory, and a fourth signal received through the second terminal in synchronization with the third signal is used by the SPI controller as data to be written into the nonvolatile memory. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the SPI controller is configured to operate in the first mode when the command indicates the first mode and in the second mode when the command indicates the second mode. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the command is a command to load data to be programmed. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the first mode is a normal SPI mode in which data to be written into the nonvolatile memory is communicated through one terminal, which is the first terminal, and the second mode is a quad SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through four terminals including the first and second terminals. ### Claim 8 (depends on 1) The memory system according to claim 1, further comprising: a third terminal, wherein the plurality of operational modes includes a third mode, in the first mode, the SPI controller uses the third terminal for data output, and not data input, in the second mode, the SPI controller uses each of the second and third terminals for data input and data output, and in the third mode, the SPI controller uses the third terminal for data input and data output, and the signal received through the second terminal is used by the SPI controller as the control signal to perform the predetermined function. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the first mode is a normal SPI mode in which data to be written into the nonvolatile memory is communicated through one terminal, which is the first terminal, the second mode is a quad SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through four terminals including the first and second terminals, and the third mode is a dual SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through two terminals, which are the first and third terminals. ### Claim 10 A method for controlling a memory system including a nonvolatile memory, a first terminal, and a second terminal with a serial peripheral interface (SPI) controller with an external controller external to the memory system in accordance with an SPI standard, the method comprising: receiving a command through the first terminal; determining an operational mode of the SPI controller to be one of a plurality of operational modes including a first mode and a second mode, based on the command; upon determining the operational mode to be the first mode, operating in the first mode in which a signal received through the second terminal is used as a control signal to perform a predetermined function; and upon determining the operational mode to be the second mode, operating in the second mode in which the signal received through the second terminal is not used as the control signal to perform the predetermined function, wherein the method further comprises, in the second mode; using a second signal of a predetermined length received through the first terminal following the command as an address of the nonvolatile memory to be accessed; and performing an operation to disable the predetermined function during reception of the second signal used as the address through the first terminal. ### Claim 11 (depends on 10) The method according to claim 10, wherein the predetermined function includes a function of pausing communication through the first terminal. ### Claim 12 (depends on 10) The method according to claim 10, wherein in the first mode, the first terminal is used for data input, and not for data output, and in the second mode, each of the first and second terminals is used for data input and data output. ### Claim 13 (depends on 10) The method according to claim 10, further comprising, in the second mode: using a third signal received through the first terminal following the address as data to be written into the nonvolatile memory and a fourth signal received through the second terminal in synchronization with the third signal as data to be written into the nonvolatile memory. ### Claim 14 (depends on 10) The method according to claim 10, wherein the command is a command to load data to be programmed. ### Claim 15 (depends on 10) The method according to claim 10, wherein the first mode is a normal SPI mode in which data to be written into the nonvolatile memory is communicated through one terminal, which is the first terminal, and the second mode is a quad SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through four terminals including the first and second terminals. ### Claim 16 (depends on 10) The method according to claim 10, wherein the memory system further includes a third terminal, the plurality of operational modes includes a third mode, in the first mode, the third terminal is used for data output, and not data input, in the second mode, each of the second and third terminals is for data input and data output, and in the third mode, the third terminal is used for data input and data output and the signal received through the second terminal is used as the control signal to perform the predetermined function. ### Claim 17 (depends on 16) The method according to claim 16, wherein the first mode is a normal SPI mode in which data to be written into the nonvolatile memory is communicated through one terminal, which is the first terminal, the second mode is a quad SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through four terminals including the first and second terminals, and the second third mode is a dual SPI mode in which data to be written into the nonvolatile memory is parallelly communicated through two terminals, which are the first and third terminals. ### Claim 18 (depends on 1) The memory system according to claim 1, wherein the command is a command to access the address of the nonvolatile memory. ### Claim 19 (depends on 10) The method according to claim 10, wherein the command is a command to access the address of the nonvolatile memory.