# US 12,182,398 B2 · Virtual network pre-arbitration for deadlock avoidance and enhanced performance

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- Number: US 12,182,398 B2
- Document ID: US12182398B2
- Status: Granted
- Kind: B2
- Application number: 18/332,831
- Filed: 2023-06-12
- Published: 2023-10-12
- Granted: 2024-12-31
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Matthew David Pierson; Daniel Wu; Kai Chirca
- Web page: https://patentgrep.com/patent/US12182398B2

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

## Claims

### Claim 1

A device comprising:
a set of interfaces configured to receive a set of memory requests that includes a first memory request and a second memory request; and
a circuit coupled to the set of interfaces that includes:
an interconnect configured to route the set of memory requests; and
an arbiter circuit configured to:
for each request of the set of memory requests, determine a respective credit cost and a respective credit count;
when the respective credit cost of the first memory request is less than or equal to the respective credit count of the first memory request, inhibit selection of the first memory request based on the respective credit count for the first memory request having fallen at or below a lower threshold and having not subsequently met or exceeded an upper threshold;
when the respective credit cost of the second memory request is less than or equal to the respective credit count of the second memory request, select the second memory request from among the set of memory requests; and
cause the second memory request to be provided over the interconnect based on the second memory request being selected.

### Claim 2 (depends on 1)

The device of claim 1 further comprising:
a cache controller that includes the set of interfaces and the circuit; and
a cache memory coupled to the cache controller, wherein the cache controller is configured to cause the second memory request to be performed using the cache memory.

### Claim 3 (depends on 1)

The device of claim 1 further comprising a cache controller that includes:
the set of interfaces;
the circuit; and
an external memory interface configured to couple to an external memory, wherein the cache controller is configured to cause the second memory request to be performed using the external memory.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
the set of interfaces is configured to receive a third memory request subsequent to the set of memory requests;
the second memory request has a first priority;
the third memory request has a second priority; and
the arbiter circuit is configured to compare the second priority to the first priority to determine whether to cause the third memory request to be provided over the interconnect before the second memory request.

### Claim 5 (depends on 1)

The device of claim 1, wherein the respective credit cost of each of the set of memory requests is based on a type associated with the respective memory request.

### Claim 6 (depends on 1)

The device of claim 1, wherein the respective credit cost of each of the set of memory requests is based on whether the respective memory request is a read request or a write request.

### Claim 7 (depends on 1)

The device of claim 1, wherein the arbiter circuit is configured to select the second memory request based on applying a sharing algorithm to a subset of the set of memory requests for which the respective credit cost is less than or equal to the respective credit count.

### Claim 8 (depends on 7)

The device of claim 7, wherein the sharing algorithm is a round robin algorithm.

### Claim 9 (depends on 1)

The device of claim 1 further comprising a set of cache tag circuits coupled to the circuit, wherein the circuit is configured to cause the second memory request to be provided to at least one cache tag circuit of the set of cache tag circuits via the interconnect.

### Claim 10

A device comprising:
a set of processor cores; and
a memory controller circuit coupled to the set of processor cores, wherein the memory controller circuit includes:
a set of interfaces configured to receive a set of memory requests that includes a first memory request;
a memory; and
a circuit coupled between the set of interfaces and the memory, wherein the circuit includes:
an interconnect; and
an arbiter circuit configured to:
determine a respective credit cost and a respective credit count for the first memory request; and
when the respective credit cost of the first memory request is less than or equal to the respective credit count of the first memory request, determine whether to inhibit selection of the first memory request based on whether the respective credit count for the first memory request has fallen at or below a lower threshold without subsequently meeting or exceeding an upper threshold.

### Claim 11 (depends on 10)

The device of claim 10, wherein:
the set of memory requests includes a second memory request; and
the arbiter circuit is configured to:
determine a respective credit cost and a respective credit count for the second memory request;
when the respective credit cost of the second memory request is less than or equal to the respective credit count of the second memory request, select the second memory request from among the set of memory requests; and
cause the second memory request to be provided over the interconnect based on the second memory request being selected.

### Claim 12 (depends on 11)

The device of claim 11, wherein:
the memory controller circuit includes an external memory interface configured to couple to an external memory, wherein the memory controller circuit is configured to cause the second memory request to be performed using the external memory.

### Claim 13 (depends on 11)

The device of claim 11, wherein:
the set of interfaces is configured to receive a third memory request subsequent to the set of memory requests;
the second memory request has a first priority;
the third memory request has a second priority; and
the arbiter circuit is configured to compare the second priority to the first priority to determine whether to cause the third memory request to be provided over the interconnect before the second memory request.

### Claim 14 (depends on 11)

The device of claim 11, wherein the arbiter circuit is configured to select the second memory request based on applying a sharing algorithm to a subset of the set of memory requests for which the respective credit cost is less than or equal to the respective credit count.

### Claim 15 (depends on 14)

The device of claim 14, wherein the sharing algorithm is a round robin algorithm.

### Claim 16

A method comprising:
receiving a set of memory requests that includes a first memory request and a second memory request;
for each request of the set of memory requests, determining a respective credit cost and a respective credit count;
determining that the respective credit cost of the first memory request is less than or equal to the respective credit count of the first memory request;
determining that the respective credit cost of the second memory request is less than or equal to the respective credit count of the second memory request;
selecting the second memory request over the first memory request based on the respective credit count for the first memory request having fallen at or below a lower threshold and the respective credit count for the first memory request having not subsequently met or exceeded an upper threshold; and
causing the second memory request to be provided over an interconnect based on the second memory request being selected.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the method comprises receiving a third memory request subsequent to the second memory request;
the second memory request has a first priority;
the third memory request has a second priority; and
the method comprises determining whether to cause the third memory request to be provided over the interconnect before the second memory request based on whether the second priority is greater than the first priority.

### Claim 18 (depends on 16)

The method of claim 16, wherein the respective credit cost of each of the set of memory requests is based on a type associated with the respective memory request.

### Claim 19 (depends on 16)

The method of claim 16 further comprising applying a sharing algorithm to a subset of the set of memory requests for which the respective credit cost is less than or equal to the respective credit count, wherein the selecting of the second memory request is further based on the sharing algorithm.

### Claim 20 (depends on 19)

The method of claim 19, wherein the sharing algorithm is a round robin algorithm.