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US 12,182,397 B2Granted
Apparatuses and methods for configurable memory array bank architectures
OwnerDean D. Gans, Shunichi Saitoinventors
Life of this patent
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Abstract
Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
Claims20
An apparatus comprising:
- a mode register configured to store a value to set a bank architecture from a plurality of bank architectures, wherein the value in the mode register is configured to be switched by changing a frequency set point between a plurality of frequency set points;
- a memory array, wherein memory banks of the memory array are configured in a bank group mode when the value comprises a first value and the memory banks of the memory array are configured in a bank mode when the value comprises a second value;
- a plurality of data busses coupled to the memory array;
- a plurality of external data terminals;
- and
- a plurality of data paths coupled between the plurality of data buses and the plurality of external terminals.
3 more elements
A method comprising:
- receiving a clock signal at a memory;
- receiving a mode register write command and a value to be written to a mode register of the memory;
- responsive to the mode register write command, writing the value to the mode register to set a frequency set point of a plurality of frequency set points of the memory;
- receiving a first read command and a first address;
- and
- receiving a second read command and a second address,
- providing first data associated with the first read command and providing second data associated with the second read command when the second read command is received at least a number of clock cycles after the first read command, the number of clock cycles based, at least in part, on a bank architecture set in the memory wherein the bank architecture is based, at least in part, on the frequency set point.
4 more elements
An apparatus comprising:
- a clock circuit configured to receive an external clock signal;
- a command decoder configured to receive a first read command and a second read command;
- an address decoder configured to receive a first address and a second address associated with the first and second read commands;
- a mode register configured to store a first value to set a bank architecture from a plurality of bank architectures, wherein the plurality of bank architectures comprises a bank mode and a bank group mode and further configured to store a second value to set a frequency set point from a plurality of frequency set points, wherein the first value is configured to be changed by changing the second value;
- and
- a memory array configured in one of the plurality of bank architectures based on the value, wherein the memory array is further configured to provide first data responsive to the first read command and to provide second data responsive to the second read command when the second read command is received at least a number of clock cycles after the first read command, wherein the number of clock cycles is based at least in part, on the bank architecture of the memory array.
3 more elements
Dependencies are inferred from the claim text.