# US 12,182,396 B2 · Performance and memory access tracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,396 B2 - Document ID: US12182396B2 - Status: Granted - Kind: B2 - Application number: 18/192,694 - Filed: 2023-03-30 - Published: 2024-10-03 - Granted: 2024-12-31 - Earliest claimed: 2023-03-30 - Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC - Applicants: Advanced Micro Devices, Inc.; ATI Technologies ULC - Inventors: Christopher J. Brennan; Akshay Lahiry; Guennadi Riguer - Web page: https://patentgrep.com/patent/US12182396B2 ## CPC - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0673: {Single storage device} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range. ## Claims ### Claim 1 A method comprising: generating a plurality of performance log entries based on observed operations; and generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries is associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range. ### Claim 2 (depends on 1) The method of claim 1, wherein each performance log entry of the performance log entries includes a set of performance statistics. ### Claim 3 (depends on 2) The method of claim 2, wherein the set of performance statistics includes information about how much data is read from or written to memory within an epoch. ### Claim 4 (depends on 2) The method of claim 2, wherein the set of performance statistics includes information about bandwidth utilization for memory or data fabric within an epoch. ### Claim 5 (depends on 1) The method of claim 1, wherein, for a performance log entry associated with an epoch, the performance log entry includes one or more pointers that point to one or more memory access log entries for the epoch. ### Claim 6 (depends on 1) The method of claim 1 further comprising processing multiple memory access log entries of the plurality of performance log entries in parallel by a plurality of compute unit execution items. ### Claim 7 (depends on 6) The method of claim 6, wherein processing the multiple memory access logs in parallel includes analyzing the multiple memory access logs to identify operational changes to improve performance. ### Claim 8 (depends on 1) The method of claim 1, wherein each memory access log entry includes statistics for memory accesses within the memory address range and for the epoch associated with the memory access log entry. ### Claim 9 (depends on 1) The method of claim 1, further comprising storing each memory access log entry and each performance log entry into a backing store. ### Claim 10 A system, comprising: a computing system; and a logger configured to: generate a plurality of performance log entries based on observed operations; and generate a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries is associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range. ### Claim 11 (depends on 10) The system of claim 10, wherein each performance log entry of the performance log entries includes a set of performance statistics. ### Claim 12 (depends on 11) The system of claim 11, wherein the set of performance statistics includes information about how much data is read from or written to memory within an epoch. ### Claim 13 (depends on 11) The system of claim 11, wherein the set of performance statistics includes information about bandwidth utilization for memory or data fabric within an epoch. ### Claim 14 (depends on 10) The system of claim 10, wherein, for a performance log entry associated with an epoch, the performance log entry includes one or more pointers that point to one or more memory access log entries for the epoch. ### Claim 15 (depends on 10) The system of claim 10, further comprising a processor configured to execute a plurality of compute unit execution items that are configured to process multiple memory access log entries of the plurality of performance log entries in parallel. ### Claim 16 (depends on 15) The system of claim 15, wherein processing the multiple memory access logs in parallel includes analyzing the multiple memory access logs to identify operational changes to improve performance. ### Claim 17 (depends on 10) The system of claim 10, wherein each memory access log entry includes statistics for memory accesses within the memory address range and for the epoch associated with the memory access log entry. ### Claim 18 (depends on 10) The system of claim 10, wherein the logger is further configured to store each memory access log entry and each performance log entry into a backing store. ### Claim 19 A non-transitory computer-readable medium storing information that, when executed by a processor, cause the processor to perform operations comprising: generating a plurality of performance log entries based on observed operations; and generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries is associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, wherein the operations further comprise storing each memory access log entry and each performance log entry into a backing store.