# US 12,182,316 B2 · Integrated circuit protection against reverse engineering > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,316 B2 - Document ID: US12182316B2 - Status: Granted - Kind: B2 - Application number: 18/153,578 - Filed: 2023-01-12 - Published: 2023-08-03 - Granted: 2024-12-31 - Earliest claimed: 2022-02-01 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Stefan Seidl; Joel Hatsch; Artur Wroblewski - Web page: https://patentgrep.com/patent/US12182316B2 ## CPC - G06F 21/75: by inhibiting the analysis of circuitry or operation - G06F 21/72: in cryptographic circuits - G06F 21/77: in smart cards - H03K 3/037: Bistable circuits - H03K 19/003: Modifications for increasing the reliability {for protection} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line. The logic path and the clock signal line are formed such that their delays are such that, depending on a value of the secret bit, a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal. ## Claims ### Claim 1 An integrated circuit, comprising: a first clocked memory element having a first data input, a first data output and a first clock input; a second clocked memory element having a second data input, a second data output and a second clock input; a logic path coupling the first data output to the second data input; a clock signal line coupling the first clock input to the second clock input; wherein delays of the logic path and the clock signal line are such that a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal; a secret bit generation circuit configured to output a secret bit whose value depends on whether a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal; and a processing circuit configured to at least one of check whether the value of the secret bit is correct and, if the value of the secret bit is not correct, signal an alarm, and use the secret bit as a bit of cryptographic key and perform a cryptographic operation using the cryptographic key. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein checking whether the value of the secret bit is correct comprises using the secret bit for an operation and checking whether a result of the operation is correct. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein checking whether the value of the secret bit is correct comprises comparing the secret bit with a reference bit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, comprising a control circuit configured to initiate a generation of the secret bit by supplying a data signal triggering the logic level change of the first clocked memory element to the first clocked memory element. ### Claim 5 (depends on 4) The integrated circuit of claim 4, comprising a test input, wherein the control circuit is configured to initiate the generation of the secret bit by supplying the data signal to the first clocked memory element via the test input. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the secret bit generation circuit is configured such that the value of the secret bit that it outputs is equal to a first predetermined bit value if a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with the same clock edge of the clock signal, and is equal to a second predetermined bit value different from the first predetermined bit value else if a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line does not affect the logic level output by the second clocked memory element with the same clock edge of the clock signal. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the secret bit generation circuit is configured such that the value of the secret bit that it outputs is equal to a first predetermined bit value if a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects the logic level output by the second clocked memory element with a clock edge coming after the next clock edge of the clock signal and is equal to a second predetermined bit value different from the first predetermined bit value else if a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line does not affect the logic level change of the second clocked memory element with the clock edge coming after the next clock edge of the clock signal. ### Claim 8 (depends on 1) An integrated circuit comprising a plurality of sub-circuits, each sub-circuit comprising a respective first clocked memory element, a respective second clocked memory element, a respective logic path and a respective clock signal line and a respective secret bit generation circuit according to the integrated circuit of claim 1, and comprising a processing circuit configured to at least one of check whether the value of the secret bits are correct and, if the value of the secret bit are not correct, signal an alarm, and form a cryptographic key from the secret bits and perform a cryptographic operation using the cryptographic key.