# US 12,182,059 B2 · Serial bus system and method

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- Number: US 12,182,059 B2
- Document ID: US12182059B2
- Status: Granted
- Kind: B2
- Application number: 18/063,453
- Filed: 2022-12-08
- Published: 2023-06-22
- Granted: 2024-12-31
- Earliest claimed: 2021-12-16
- Assignees: STMicroelectronics (Research & Development) Limited
- Applicants: STMicroelectronics (Research & Development) Limited
- Inventors: Jeffrey M. Raynor; Sergio Miguez Aparicio; Benjamin Thomas Sarachi
- Web page: https://patentgrep.com/patent/US12182059B2

## CPC

- G06F 13/4291: {using a clocked protocol}
- G06F 13/20: for access to input/output bus
- G06F 13/4068: {Electrical coupling}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G06F 13/4077: {Precharging or discharging}
- H04L 1/0083: {Formatting with frames or packets; Protocol or part of protocol for error control}
- H04L 25/0264: {Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878)}
- H04L 69/22: Parsing or analysis of headers
- H03M 5/02: Conversion to or from representation by pulses
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.

## Claims

### Claim 1

A system comprising:
a primary device comprising:
a first port configured to be connected to a first port of a secondary device; and
a second port configured to be connected to a second port of the secondary device, wherein:
the first port of the primary device is configured to provide a clock signal determining, for each bit transmission between the primary device and the secondary device, a succession of a first phase, a second phase, a third phase and a fourth phase,
the primary device is configured to load its second port to a first potential different from a reference potential during a data bit transmission between the primary device and the secondary device,
the primary device is configured to put its second port in a high impedance state during the second and fourth phases of the data bit transmission between the primary device and the secondary device, and
the primary device is configured to put its second port in the high impedance state during the third phase of a data bit transmission from the secondary device to the primary device.

### Claim 2 (depends on 1)

The system of claim 1, further comprising the secondary device including:
the first port connected to a first port of the primary device; and
the second port connected to a second port of the primary device, wherein:
the first port of the secondary device is configured to receive the clock signal from the primary device,
the secondary device is configured to put its second port in the high impedance state during the first, second and fourth phases of each bit transmission between the primary device and the secondary device, and
the secondary device is configured, during the third phase of the data bit transmission from the secondary device to the primary device, to discharge its second port to the reference potential when a value of the data bit transmission from the secondary device to the primary device has a first value and to leave its second port in the high impedance state when the value of the data bit transmission from the secondary device to the primary device has a second value.

### Claim 3 (depends on 2)

The system of claim 2, wherein the primary device is configured, during the fourth phase of the data bit transmission from the secondary device to the primary device, to determine the value of the data bit transmission from the secondary device to the primary device based on a potential on its second port during the fourth phase.

### Claim 4 (depends on 2)

The system of claim 2, wherein, during the third phase of a data transmission from the primary device to the secondary device:
the secondary device is configured to put its second port in the high impedance state; and
the primary device is configured to apply the reference potential on its second port when the value of the data bit transmission from the primary device to the secondary device is the first value and to put its second port in the high impedance state when the value of the data bit transmission from the primary device to the secondary device is the second value.

### Claim 5 (depends on 4)

The system of claim 4, wherein, during the fourth phase of the data bit transmission from the primary device to the secondary device, the secondary device is configured to determine the value of the data bit transmission from the primary device to the secondary device based on a potential on its second port during the fourth phase.

### Claim 6 (depends on 2)

The system of claim 2, wherein the primary device is configured to apply the reference potential to its second port during the first phase of a control bit transmission from the primary device to the secondary device.

### Claim 7 (depends on 6)

The system of claim 6, wherein:
the secondary device is further configured to leave its second port in the high impedance state during the third and the fourth phase of the control bit transmission from the primary device to the secondary device, and
the primary device is further configured, during the second, third and fourth phases of the control bit transmission from the primary device to the secondary device, to leave its second port in the high impedance state or to discharge its second port to the reference potential.

### Claim 8 (depends on 2)

The system of claim 2, wherein:
the primary device is configured to load its second port to the first potential during the first phase of an acknowledgment bit transmission from the secondary device to the primary device; and
the secondary device is configured, during the third phase of the acknowledgment bit transmission from the secondary device to the primary device, to discharge its second port to the reference potential when a value of the acknowledgment bit transmission from the secondary device to the primary device indicates a valid acknowledgment and to leave its second port in the high impedance state when the value of the acknowledgment bit transmission from the secondary device to the primary device indicates an invalid acknowledgement.

### Claim 9 (depends on 8)

The system of claim 8, wherein the primary device is configured:
to leave its second port at the high impedance state during the second phase, the third phase and the fourth phase of the acknowledgment bit transmission from the secondary device to the primary device; and
during the fourth phase of the acknowledgment bit transmission from the secondary device to the primary device, to determine whether an acknowledgment represented by the value of the acknowledgment bit transmission from the secondary device to the primary device is valid based on a potential on its second port during the fourth phase.

### Claim 10 (depends on 2)

The system of claim 2, wherein, at the beginning of the first phase, the second phase, the third phase and the fourth phase of each bit transmission between the primary device and the secondary device, the primary device is configured to provide an edge of a first type of the clock signal among a rising edge type and a falling edge type.

### Claim 11 (depends on 2)

The system of claim 2, wherein the primary device is configured to provide only one pulse of the clock signal for each bit transmission between the primary device and the secondary device, the beginning of the pulse indicating the beginning of the third phase of each bit transmission between the primary device and the secondary device and the end of the pulse indicating the beginning of the fourth phase of each bit transmission between the primary device and the secondary device.

### Claim 12 (depends on 11)

The system of claim 11, wherein a duration of each pulse of the clock signal is determined by a discharge time of the second ports of the devices from the first potential to the reference potential.

### Claim 13 (depends on 1)

The system of claim 1, wherein the primary device is configured, during the fourth phase of the data bit transmission from the secondary device to the primary device, to determine a value of the data bit transmission from the secondary device to the primary device based on a potential on its second port during the fourth phase.

### Claim 14 (depends on 1)

The system of claim 1, wherein the primary device is configured to apply the reference potential to its second port during the first phase of a control bit transmission from the primary device to the secondary device.

### Claim 15 (depends on 1)

The system of claim 1, wherein the primary device is configured to load its second port to the first potential during the first phase of an acknowledgment bit transmission from the secondary device to the primary device.

### Claim 16

A secondary device comprising:
a first port configured to be connected to a first port of a primary device; and
a second port configured to be connected to a second port of the primary device, wherein:
the first port of the secondary device is configured to receive a clock signal determining, for each bit transmission between the primary device and the secondary device, a succession of a first phase, a second phase, a third phase and a fourth phase;
the secondary device is configured to put its second port in a high impedance state during the first, second and fourth phases of each bit transmission between the primary device and the secondary device; and
the secondary device is configured, during the third phase of a data bit transmission from the secondary device to the primary device, to discharge its second port to a reference potential when a value of the data bit transmission from the secondary device to the primary device has a first value and to leave its second port in the high impedance state when the value of the data bit transmission from the secondary device to the primary device has a second value.

### Claim 17 (depends on 16)

The device of claim 16, wherein, during the third phase of a data bit transmission from the primary device to the secondary device, the secondary device is configured to put its second port in the high impedance state.

### Claim 18 (depends on 16)

The device of claim 16, wherein the secondary device is configured, during the third phase of an acknowledgment bit transmission from the secondary device to the primary device, to discharge its second port to the reference potential when a value of the acknowledgment bit transmission from the secondary device to the primary device indicates a valid acknowledgment and to leave its second port in the high impedance state when the value of the acknowledgment bit transmission from the secondary device to the primary device indicates an invalid acknowledgement.

### Claim 19

A method of transmitting a bit between a secondary device and a primary device, the secondary device comprising a first port connected to a first port of the primary device and a second port connected to a second port of the primary device, wherein:
providing, by the primary device, a clock signal to the first port of the secondary device, the clock signal determining, for each bit transmission between the primary device and the secondary device, a succession of a first phase, a second phase, a third phase and a fourth phase;
during the first phase of a data bit transmission between the primary device and the secondary device, loading the second port of the primary device to a first potential different from a reference potential;
during the first phase of the data bit transmission between the primary device and the secondary device, leaving the second port of the secondary device in a high impedance state;
during the second phase of the data bit transmission between the primary device and the secondary device, leaving the second port of the primary device in the high impedance state;
during the third phase of a data bit transmission from the secondary device to the primary device, leaving the second port of the primary device in the high impedance state; and
during the fourth phase of the data bit transmission between the primary device and the secondary device, determining a value for the data bit transmitted between the primary device and the secondary device based on a potential on the second port of the primary device and the second port of the secondary device.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
during the first phase of the data bit transmission between the primary device and the secondary device, leaving the second port of the secondary device in the high impedance state; and
during the third phase of the data bit transmission from the secondary device to the primary device, discharging the second port of the secondary device to the reference potential to transmit a first value, and leaving the second port of the secondary device in the high impedance state to transmit a second value.