# US 12,182,056 B1 · Multi level loopback to enable automated testing of standalone connectivity controller

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- Number: US 12,182,056 B1
- Document ID: US12182056B1
- Status: Granted
- Kind: B1
- Application number: 18/134,419
- Filed: 2023-04-13
- Granted: 2024-12-31
- Earliest claimed: 2023-04-13
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Saleem Chisty Mohammad
- Web page: https://patentgrep.com/patent/US12182056B1

## CPC

- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 11/221: {to test buses, lines or interfaces, e.g. stuck-at or open line faults}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of testing a connectivity controller includes, in part, setting a configuration register disposed in the connectivity controller to a first value; causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value; returning data received by the second component, via the first component, for storage in a second section of the memory; comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and verifying the test if the first data matches the returned data.

## Claims

### Claim 1

A method of testing a connectivity controller, the method comprising:
setting a configuration register disposed in the connectivity controller to a first value;
causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value;
returning data received by the second component, via the first component, for storage in a second section of the memory;
comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and
verifying the test if the first data matches the returned data.

### Claim 2 (depends on 1)

The method of claim 1, wherein the connectivity controller is one or more of a Universal Serial Bus 4 (USB4) host controller and a USB4 device controller.

### Claim 3 (depends on 2)

The method of claim 2, wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first component is a USB3 media access controller.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second component is a USB3 link controller.

### Claim 6 (depends on 2)

The method of claim 2 further comprising:
validating, by the first component, that a packet represented by the first data conform to the USB4 communications protocols; and
validating, by the second component, that a packet represented by the data returned to the second section of the memory conform the USB4 communications protocol.

### Claim 7 (depends on 2)

The method of claim 2 further comprising:
setting the configuration register to a second value;
causing a second data stored in the first section of the first memory to be forwarded to a physical access layer (PHY) of the USB4 controller;
returning data from the PHY for storage in the second section of the memory;
comparing the second data to the data returned from the PHY and stored in the second section of the memory; and
verifying the test if the second data matches the data returned from the PHY.

### Claim 8 (depends on 2)

The method of claim 2, the method further comprising:
setting a direction bit of a packet represented by the first data to a first logic level; and
setting a direction bit of a packet represented by the returned data to a second logic level.

### Claim 9

A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:
set a configuration register disposed in a connectivity controller to a first value;
cause a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value;
return data received by the second component, via the first component, for storage in a second section of the memory;
compare the first data to the data returned and stored in the second section of the memory; and
verify the test if the first data matches the return data.

### Claim 10 (depends on 9)

The system of claim 9, wherein the connectivity controller is one or more of a USB4 host controller and a USB4 device controller.

### Claim 11 (depends on 10)

The system of claim 10, wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

### Claim 12 (depends on 11)

The hardware emulation system of claim 11, wherein the first component is a USB3 media access controller.

### Claim 13 (depends on 12)

The hardware emulation system of claim 12, wherein the second component is a USB3 link controller.

### Claim 14 (depends on 10)

The system of claim 10, wherein the USB4 controller comprises a Peripheral Component Interconnect Express (PCIe) controller.

### Claim 15 (depends on 10)

The system of claim 10, wherein the instruction further causes the processor to:
set the configuration register to a second value;
cause a second data stored in the first section of the first memory to be forwarded to a physical access layer (PHY) of the USB4 controller;
return data from the PHY for storage in the second section of the memory;
compare the second data to the data returned from the PHY and stored in the second section of the memory; and
verify the test if the second data matches the data returned from the PHY.

### Claim 16 (depends on 10)

The system of claim 10, wherein the instructions further cause the processor to:
set a direction bit of a packet represented by the first data to a first logic level; and
set a direction bit of a packet represented by the second data to a second logic level.

### Claim 17

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
set a configuration register disposed in a USB4 controller to a first value;
cause a first data stored in a first section of a memory associated with the USB4 controller to be forwarded and pass through at least a first component of the USB4 controller and a second component of the USB4 controller, in sequence, in response to the first value;
return data received by the second component, via the first component, for storage in a second section of the memory;
compare the first data to the data returned and stored in the second section of the memory; and
verify the test if the first data matches the return data.

### Claim 18 (depends on 17)

The non-transitory computer readable medium of claim 17, wherein the USB4 controller is one or more of a USB4 host controller and a USB4 device controller.

### Claim 19 (depends on 17)

The non-transitory computer readable medium of claim 17, wherein the USB4 controller is configured to process both USB3 generation T packets and USB3 generation X packets.

### Claim 20 (depends on 19)

The non-transitory computer readable medium of claim 19, wherein the instructions further cause the processor:
set a direction bit of a packet represented by the first data to a first logic level; and
set a direction bit of a packet represented by the returned data to a second logic level.