# US 12,182,052 B2 · Slave-initiated communications over a single-wire bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,052 B2 - Document ID: US12182052B2 - Status: Granted - Kind: B2 - Application number: 18/154,127 - Filed: 2023-01-13 - Published: 2023-07-20 - Granted: 2024-12-31 - Earliest claimed: 2022-01-20 - Assignees: Qorvo US, Inc. - Applicants: Qorvo US, Inc. - Inventors: Christopher Truong Ngo; Alexander Wayne Hietala; Nadim Khlat - Web page: https://patentgrep.com/patent/US12182052B2 ## CPC - G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)} - H04L 12/403: with centralised control, e.g. polling - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed. ## Claims ### Claim 1 A single-wire bus apparatus comprising: a master circuit coupled to a single-wire bus consisting of one wire; and a plurality of slave circuits each coupled to the single-wire bus and uniquely identified by a unique slave identification (USID) comprising multiple bits; wherein one or more slave circuits among the plurality of slave circuits are each configured to: assert a wakeup current mode signaling (CMS) on the single-wire bus to indicate a request to communicate a data telegram over the single-wire bus in response to a respective data trigger unknown to the master circuit; receive a plurality of pulse-width modulation (PWM) symbols via the single-wire bus in response to asserting the wakeup CMS; determine whether the request is successful based on the plurality of received PWM symbols; and communicate the data telegram over the single-wire bus in response to determining that the request is successful. ### Claim 2 (depends on 1) The single-wire bus apparatus of claim 1, wherein the master circuit is configured to: detect the wakeup CMS asserted by the one or more slave circuits; transmit a start-of-sequence (SOS) sequence over the single-wire bus in response to detecting the wakeup CMS asserted by the one or more slave circuits; and transmit the plurality of PWM symbols via the single-wire bus in an arbitration interval after transmitting the SOS sequence. ### Claim 3 (depends on 2) The single-wire bus apparatus of claim 2, wherein the plurality of PWM symbols comprises a priority symbol and a plurality of USID bit symbols succeeding the priority symbol. ### Claim 4 (depends on 3) The single-wire bus apparatus of claim 3, wherein the master circuit is further configured to: modulate the priority symbol and a respective one of the plurality of USID bit symbols to represent a binary one in response to detecting a bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols; and modulate the priority symbol and the respective one of the plurality of USID bit symbols to represent a binary zero in response to not detecting the bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols. ### Claim 5 (depends on 3) The single-wire bus apparatus of claim 3, wherein the request is determined to be successful by a respective one of the one or more slave circuits if the plurality of USID bit symbols collectively indicate the multiple bits in the USID that uniquely identify the respective one of the one or more slave circuits. ### Claim 6 (depends on 5) The single-wire bus apparatus of claim 5, wherein each of the plurality of USID bit symbols represents a respective one of the multiple bits in the USID and a first one of the plurality of USID bit symbols immediately succeeding the priority symbol represents a most significant bit (MSB) of the USID. ### Claim 7 (depends on 6) The single-wire bus apparatus of claim 6, wherein, in a first attempt to contend for the single-wire bus, the respective one of the one or more slave circuits is further configured to: assert a bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to one; and not assert the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to zero. ### Claim 8 (depends on 7) The single-wire bus apparatus of claim 7, wherein the respective one of the one or more slave circuits is further configured not to assert the bit indication CMS in the priority symbol in the first attempt to contend for the single-wire bus. ### Claim 9 (depends on 5) The single-wire bus apparatus of claim 5, wherein the respective one of the one or more slave circuits is further configured not to assert a bit indication CMS in the priority symbol when the request is determined to be successful. ### Claim 10 (depends on 6) The single-wire bus apparatus of claim 6, wherein, in response to an unsuccessful attempt to contend for the single-wire bus, the respective one of the one or more slave circuits is further configured to: assert a bit indication CMS in the priority symbol; assert the bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to one; and not assert the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID that uniquely identifies the respective one of the one or more slave circuits is equal to zero. ### Claim 11 (depends on 1) The single-wire bus apparatus of claim 1, wherein each of the plurality of slave circuits is configured to harvest power via the single-wire bus while one of the plurality of slave circuits communicates the data telegram over the single-wire bus. ### Claim 12 A method for supporting slave-initiated communications to a master circuit over a single-wire bus comprising: asserting a wakeup current mode signaling (CMS) on the single-wire bus to indicate a request to communicate a data telegram over the single-wire bus in response to a respective data trigger unknown to the master circuit; receiving a plurality of pulse-width modulation (PWM) symbols via the single-wire bus in response to asserting the wakeup CMS; determining whether the request is successful based on the plurality of received PWM symbols; and communicating the data telegram over the single-wire bus in response to determining that the request is successful. ### Claim 13 (depends on 12) The method of claim 12, further comprising: detecting the wakeup CMS; transmitting a start-of-sequence (SOS) sequence over the single-wire bus in response to detecting the wakeup CMS; and transmitting the plurality of PWM symbols via the single-wire bus in an arbitration interval after transmitting the SOS sequence. ### Claim 14 (depends on 13) The method of claim 13, further comprising: modulating a priority symbol and a respective one of a plurality of USID bit symbols succeeding the priority symbol in the plurality of PWM symbols to represent a binary one in response to detecting a bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols; and modulating the priority symbol and the respective one of the plurality of USID bit symbols to represent a binary zero in response to not detecting the bit indication CMS in the priority symbol and the respective one of the plurality of USID bit symbols. ### Claim 15 (depends on 14) The method of claim 14, further comprising determining the request as being successful if the plurality of USID bit symbols collectively indicates multiple bits in the USID that uniquely identify a respective one of one or more slave circuits. ### Claim 16 (depends on 15) The method of claim 15, further comprising, in a first attempt to contend for the single-wire bus: asserting a bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID is equal to one; and not asserting the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID is equal to zero. ### Claim 17 (depends on 16) The method of claim 16, further comprising not asserting the bit indication CMS in the priority symbol in the first attempt to contend for the single-wire bus. ### Claim 18 (depends on 15) The method of claim 15, further comprising not asserting a bit indication CMS in the priority symbol when the request is determined to be successful. ### Claim 19 (depends on 15) The method of claim 15, further comprising, in response to an unsuccessful attempt to contend for the single-wire bus: asserting a bit indication CMS in the priority symbol; asserting the bit indication CMS in a respective one of the plurality of USID bit symbols if a respective one of the multiple bits in the USID is equal to one; and not asserting the bit indication CMS in the respective one of the plurality of USID bit symbols if the respective one of the multiple bits in the USID is equal to zero. ### Claim 20 (depends on 12) The method of claim 12, further comprising harvesting power via the single-wire bus while one of a plurality of slave circuits communicates the data telegram over the single-wire bus. ### Claim 21 A wireless device comprising a single-wire bus apparatus, the single-wire bus apparatus comprises: a master circuit coupled to a single-wire bus consisting of one wire; and a plurality of slave circuits each coupled to the single-wire bus and uniquely identified by a unique slave identification (USID) comprising multiple bits; wherein one or more slave circuits among the plurality of slave circuits are each configured to: assert a wakeup current mode signaling (CMS) on the single-wire bus to indicate a request to communicate a data telegram over the single-wire bus in response to a respective data trigger unknown to the master circuit; receive a plurality of pulse-width modulation (PWM) symbols via the single-wire bus in response to asserting the wakeup CMS; determine whether the request is successful based on the plurality of received PWM symbols; and communicate the data telegram over the single-wire bus in response to determining that the request is successful.