# US 12,182,051 B1 · Multi-purpose IO pads/bumps on semiconductor chips to maximize chip-to-chip data connectivity

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- Number: US 12,182,051 B1
- Document ID: US12182051B1
- Status: Granted
- Kind: B1
- Application number: 16/986,004
- Filed: 2020-08-05
- Granted: 2024-12-31
- Earliest claimed: 2019-08-05
- Assignees: NuConcepts Holdings LLC
- Applicants: Nuconcepts Holdings LLC
- Inventors: Behzad Bahadori
- Web page: https://patentgrep.com/patent/US12182051B1

## CPC

- G06F 13/4063: {Device-to-bus coupling}
- G06F 13/38: Information transfer, e.g. on bus (G06F13/14 takes precedence)
- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Multi-purpose interface bumps on semiconductor chips may be used to optimize chip-to-chip data connectivity, including for example high speed chip-to-chip interfaces using fine-pitched bumps adaptable to interfaces with standard bumps without loss of total data rate. A chip with fine-pitch pads for μ-bumps may be connected to an organic package substrate with every other pad populated with a bump and connected to the organic package substrate, while adjacent pads are not populated with bumps and are deactivated. Total number of active bumps to 1/N for each data interface block, and the total bandwidth may be maintained by increasing the active bump data rate by N-times.

## Claims

### Claim 1

A data interface block on a first semiconductor chip comprising pads configurable to transfer a target data throughput either over N data lanes, where N is an integer greater than zero, with each of the N data lanes transferring 1/N of the target data throughput, wherein N fine-pitched bumps deposited on the pads are used to connect the N data lanes to a second semiconductor chip, or over a high-speed data lane transferring the target data throughput when a coarse-pitched bump on one of the pads is used to connect the high-speed data lane to the second semiconductor chip, wherein the data interface block further comprising N low-speed transmitter plus one high-speed transmitter and/or N low-speed receivers plus one high-speed receiver, wherein, when the data interface is connected to the second semiconductor chip over N data lanes using the N fine-pitch bumps, the N low-speed transmitters and/or N low-speed receivers are activated or connected to the fine-pitched bumps, with the high-speed transmitter and/or receiver deactivated or not connected to any bump.

### Claim 2 (depends on 1)

The data interface block of claim 1, wherein any of the N low-speed transmitters and/or N low-speed receivers are a low speed transceiver, and the high-speed transmitter and/or high-speed receiver is a high-speed transceiver.

### Claim 3 (depends on 1)

The data interface block of claim 1, comprising N transmitters and/or N receivers that are placed together at a fine pitch and a common N:1 multiplexer and/or 1:N demultiplexer, wherein the N:1 multiplexer is configurable to connect to the N transmitters and multiplex their outputs to deliver a high-speed output at N times the data rate of each transmitter, and the 1:N demultiplexer configurable to connected to the N receivers inputs, and demultiplex a high-speed input to deliver N signals at 1/N the data rate of the high-speed input to the N receivers, wherein, if the data interface block is connected to the second semiconductor chip over N data lanes using N fine-pitch bumps, the N transmitters and/or N receivers are directly connected to the fine-pitched bumps.

### Claim 4 (depends on 1)

The data interface block of claim 1 comprising N transmitters and/or N receivers that are placed together at a fine pitch and a common N:1 multiplexer and/or 1:N demultiplexer, where the N:1 multiplexer is configurable to connect to the N transmitters and multiplex their outputs to deliver a high-speed output at N times a data rate of each transmitter, and the 1:N demultiplexer configurable to connected to the N receivers inputs, and demultiplex a high-speed input to deliver N signals at 1/N a data rate of the high-speed input to the N receivers, wherein, if the data interface block is connected to the other semiconductor chip over one data lane using a single coarse-pitch bump, the single coarse-pitched bump is connected to the N:1 multiplexer and/or the 1:N demultiplexer.

### Claim 5 (depends on 1)

The data interface block of claim 1 comprising N transmitters and/or N receivers that are placed together at a fine pitch, wherein, if the data interface block is connected to the second semiconductor chip over N data lanes using N fine-pitch bumps, the N transmitters and/or N receivers are directly connected to the fine-pitched bumps.

### Claim 6 (depends on 1)

The data interface block of claim 1 comprising N transmitters and/or N receivers that are placed together at a fine pitch, wherein, if the data interface block is connected to the second semiconductor chip over one data lane using a single coarse-pitch bump, the single coarse-pitched bump is connected to all N transmitters outputs where N transmitters outputs are time-multiplexed by substantially equally-spaced clock phases, each clocking a transmitter, to generate a high-speed output signal at N times each transmitter output, and/or the single coarse-pitched bump is connected to all N receivers inputs where a high-speed input signal is time-demultiplexed by equally-spaced clock phases, each clocking a receiver, to generate N received signals at 1/N the rate of the high-speed input signal.

### Claim 7

A data interface block on a first semiconductor chip comprising pads configurable to transfer a target data throughput either over N data lanes, where N is an integer greater than zero, with each of the N data lanes transferring 1/N of the target data throughput, wherein N fine-pitched bumps deposited on the pads are used to connect the N data lanes to a second semiconductor chip, or over a high-speed data lane transferring the target data throughput when a coarse-pitched bump on one of the pads is used to connect the high-speed data lane to the second semiconductor chip, the data interface block further comprising N low-speed transmitters plus one high-speed transmitter and/or N low-speed receivers plus one high-speed receiver, wherein, when the data interface block is connected to the other semiconductor chip over the single high-speed data lane using a single coarse-pitch bump, the high-speed transmitter and/or the high-speed receiver are activated or connected to the coarse-pitched bump, with the N low-speed transmitters and/or receivers deactivated or not connected to any bump.

### Claim 8 (depends on 7)

The data interface block of claim 7, wherein any of the N low-speed transmitter and/or receivers, the high speed transmitter, or the high-speed receiver is a transceiver.