# US 12,182,050 B2 · Systems and methods for aligning received data

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- Number: US 12,182,050 B2
- Document ID: US12182050B2
- Status: Granted
- Kind: B2
- Application number: 17/032,560
- Filed: 2020-09-25
- Published: 2021-01-14
- Granted: 2024-12-31
- Earliest claimed: 2020-09-25
- Assignees: Altera Corporation
- Applicants: Intel Corporation
- Inventors: Hazem Mohamed Taher Nouh; Choon Yee Tan
- Web page: https://patentgrep.com/patent/US12182050B2

## CPC

- G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4295: {using an embedded synchronisation}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present application is directed to an electronic device that includes a receiver configured to receive data from a second electronic device. The data includes a plurality of blocks, and each block of the plurality of blocks comprises a sync header. The receiver is also configured to align the data by performing 2 to 1 multiplexing and output the aligned data.

## Claims

### Claim 1

An electronic device comprising:
a receiver comprising:
gearbox circuitry comprising a data buffer, wherein the gearbox circuitry is configured to:
receive data from a second electronic device, wherein the data comprises a plurality of blocks, wherein each block of the plurality of blocks comprises a sync header; and
store a portion of the data in a particular configuration in the data buffer; and
sync header detection and alignment circuitry comprising multiplexer circuitry, wherein the sync header detection and alignment circuitry is configured to:
determine a location of the sync header;
determine an adjustment to be made based on the location of the sync header; and
provide an indication of the adjustment to the gearbox circuitry; and
align the data by performing 2 to 1 multiplexing via the multiplexer circuitry; and
output the aligned data.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the gearbox circuitry is configured to store the portion of the data in the particular configuration based on the indication of the adjustment.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the gearbox circuitry is configured to output semi-aligned data comprising at least one complete sync header.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the sync header detection and alignment circuitry comprises the multiplexer circuitry configured to:
receive the semi-aligned data; and
generate the aligned data by performing the 2 to 1 multiplexing.

### Claim 5 (depends on 4)

The electronic device of claim 4, wherein:
the sync header detection and alignment circuitry comprises a data register configured to store a portion of previous data; and
the multiplexer circuitry receives the portion of the previous data.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the aligned data comprises the portion of the previous data.

### Claim 7 (depends on 5)

The electronic device of claim 5, wherein the data register is configured to store only a single bit of data.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the electronic device comprises a programmable logic device.

### Claim 9 (depends on 8)

The electronic device of claim 8, wherein the programmable logic device comprises a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the multiplexer circuitry is configured to:
determine a configuration of the data based on a registered bit of the data; and
align the data based on the configuration.

### Claim 11 (depends on 1)

The electronic device of claim 1, wherein the multiplexer circuitry is configured to receive two bits of the data and output one bit of the data.

### Claim 12 (depends on 1)

The electronic device of claim 1, wherein the aligned data comprises the sync header in a same bit position at each block of the plurality of blocks.

### Claim 13 (depends on 1)

The electronic device of claim 1, wherein the multiplexer circuitry is configured to receive 133 bits of the data and output 132 bits of the aligned data.