# US 12,182,047 B2 · Chip-to-chip interface of a multi-chip module (MCM)

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- Number: US 12,182,047 B2
- Document ID: US12182047B2
- Status: Granted
- Kind: B2
- Application number: 17/996,594
- Filed: 2020-12-26
- Published: 2023-07-27
- Granted: 2024-12-31
- Earliest claimed: 2020-06-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kameran Azadet; Wee Liew; Ramani Tatikola; Edwin Thaller; Patrick Torta; Yu-Shan Wang; Georg Weber; James Yoder
- Web page: https://patentgrep.com/patent/US12182047B2

## CPC

- G06F 13/36: for access to common bus or bus system
- H10W 90/00: Package configurations
- G06F 13/4273: {using a clocked protocol}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- G06F 2213/40: Bus coupling
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/07254: {changes in dispositions}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

## Claims

### Claim 1

A chip-to-chip interface of a multi-chip module (MCM) that enables a transfer of data signals between chips of the MCM including a first chip and a second chip, comprising:
bidirectional data links configured to transmit data signals and a direction indicator bit between the first chip and the second chip,
wherein the direction indicator bit switches a direction of the bidirectional data links in real-time;
a clock link configured to transmit a clock signal common to the bidirectional data links between the first chip and the second chip,
wherein the bidirectional data links and the clock link are comprised of conductive traces between the first chip and the second chip and laid out to be of substantially equal length;
a decoder configured to output a clock delay signal based upon a delay control signal; and
a clock driver circuit having a digitally programmable clock signal delay that is based upon the clock delay signal, which prevents the clock signal from including multiple rising edges for a single transmission,
wherein a timing of the clock signal is adjusted in response to the digitally programmable clock signal delay.

### Claim 2 (depends on 1)

The chip-to-chip interface of claim 1, wherein the direction indicator bit is encoded in a redundant bit of the data signals.

### Claim 3 (depends on 1)

The chip-to-chip interface of claim 1, wherein at least one of the bidirectional data links is dedicated to transmit the direction indicator bit.

### Claim 4 (depends on 1)

The chip-to-chip interface of claim 1, wherein the clock signal delay is programmable to align an edge of the clock signal with a middle of an eye pattern of the data signal.

### Claim 5 (depends on 1)

The chip-to-chip interface of claim 1, wherein the clock signal delay is programmed before data signal transmission.

### Claim 6 (depends on 1)

The chip-to-chip interface of claim 1, wherein the clock signal delay is programmed during operation and based on a measured temperature or voltage, or a measured delay in a reference circuit.

### Claim 7 (depends on 1)

The chip-to-chip interface of claim 1, wherein the clock signal delay is Gray-encoded.

### Claim 8 (depends on 1)

The chip-to-chip interface of claim 1, further comprising:
a synchronization link configured to transmit a synchronization pulse to synchronize a deserializer of one of the first or second chip with a serializer of the other one of the first or second chip.

### Claim 9 (depends on 8)

The chip-to-chip interface of claim 8, wherein a length of the synchronization pulse is configurable to carry additional information between the first and the second chip.

### Claim 10 (depends on 1)

The chip-to-chip interface of claim 1, further comprising:
conductive bumps, which connect the bidirectional data links and the clock link between the first and the second chip, provided on each of the first and the second chip with a symmetrical mapping layout.

### Claim 11 (depends on 1)

The chip-to-chip interface of claim 1, wherein the data signal comprises at least one redundant bit for error correction.

### Claim 12 (depends on 1)

The chip-to-chip interface of claim 1, wherein the bidirectional data links and the clock link are unterminated.

### Claim 13 (depends on 1)

The chip-to-chip interface of claim 1, wherein the bidirectional data links and the clock link are provided on a package substrate directly.

### Claim 14 (depends on 1)

The chip-to-chip interface of claim 1, wherein the bidirectional data links and the clock link are provided on an interposer or bridge die.

### Claim 15 (depends on 1)

The chip-to-chip interface of claim 1, further comprising:
a common power supply shared by the first and the second chip.

### Claim 16 (depends on 1)

The chip-to-chip interface of claim 1, wherein the bidirectional data links comprise a single channel.

### Claim 17 (depends on 16)

The chip-to-chip interface of claim 16, wherein the chip-to-chip interface comprises a plurality of channels.

### Claim 18 (depends on 1)

The chip-to-chip interface of claim 1, wherein the timing of the clock signal is adjusted during operation in response to a measured temperature, a measured voltage, or a measured delay in a reference circuit, and
wherein the adjustment of the clock signal is based upon a Gray-encoded clock signal delay.

### Claim 19 (depends on 1)

The chip-to-chip interface of claim 1, wherein the clock driver circuit is configured to adjust the clock signal delay over a series of steps in response to the clock delay signal, which is encoded such that the clock signal delay is adjusted at each one of the series of steps in accordance with a single bit change of the clock delay signal.

### Claim 20 (depends on 1)

The chip-to-chip interface of claim 1, wherein the multiple rising edges for the single transmission comprise delay glitches.

### Claim 21

A multi-chip module (MCM), comprising:
a first chip;
a second chip; and
a chip-to-chip interface that enables a transfer of data signals between the first chip and the second chip, comprising:
bidirectional data links configured to transmit data signals and a direction indicator bit between the first chip and the second chip,
wherein the direction indicator bit switches a direction of a data signal transmission in real-time;
a clock link configured to transmit a clock signal common to the bidirectional data links between the first chip and the second chip,
wherein the bidirectional data links and the clock link are comprised of conductive traces between the first and second chips and laid out to be of substantially equal length;
a decoder configured to output a clock delay signal based upon a delay control signal; and
a clock driver circuit having a digitally programmable clock signal delay that is based upon the clock delay signal, which prevents the clock signal from including multiple rising edges for a single transmission,
wherein a timing of the clock signal is adjusted in response to the digitally programmable clock signal delay.

### Claim 22 (depends on 21)

The MCM of claim 21, wherein the direction indicator bit is encoded in a redundant bit of the data signals.

### Claim 23 (depends on 21)

The MCM of claim 21, wherein at least one of the bidirectional data links is dedicated to transmit the direction indicator bit.

### Claim 24 (depends on 21)

The MCM of claim 21, wherein the chip-to-chip interface further comprises:
a synchronization link configured to transmit a synchronization pulse to synchronize a deserializer of one of the first or the second chip with a serializer of the other one of the first or the second chip.

### Claim 25 (depends on 21)

The MCM of claim 21, further comprising:
conductive bumps, which connect the bidirectional data link and the clock link between the first and the second chip, provided on each of the first and the second chip with a symmetrical mapping layout.

### Claim 26 (depends on 21)

The MCM of claim 21, further comprising:
a package substrate on which the bidirectional data link and the clock link are directly provided.

### Claim 27 (depends on 21)

The MCM of claim 21, further comprising:
an interposer or bridge die on which the bidirectional data link and the clock link are provided.

### Claim 28 (depends on 21)

The MCM of claim 21, further comprising:
a common power supply shared by the first and the second chip.