# US 12,182,045 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,045 B2 - Document ID: US12182045B2 - Status: Granted - Kind: B2 - Application number: 18/152,582 - Filed: 2023-01-10 - Published: 2023-09-21 - Granted: 2024-12-31 - Earliest claimed: 2022-03-18 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kazuaki Terashima; Atsushi Nakamura; Rajesh Ghimire - Web page: https://patentgrep.com/patent/US12182045B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory. ## Claims ### Claim 1 A semiconductor device that executes neural network processing, comprising: n (n is an integer that is two or more) number of multiplier accumulators configured to multiply and accumulate pieces of input data and parameters; one or a plurality of memories configured to store the pieces of input data and the parameters; a first DMA (Direct Memory Access) controller configured to transfer the parameters stored in the memory to the n number of multiplier accumulators; a second input-side DMA controller configured to transfer the pieces of input data stored in the memory to the n number of multiplier accumulators, by use of n number of channels, respectively, and cause the n number of multiplier accumulators to perform calculations and to thereby output corresponding pieces of normal output data serving as the calculation results; a dummy circuit configured to output dummy data determined in advance to at least one or more of the n number of multiplier accumulators, thereby causing the at least one or more of the n number of multiplier accumulators to perform a dummy calculation and to output dummy output data serving as the dummy calculation result; and a second output-side DMA controller configured to transfer the respective pieces of normal output data from the n number of multiplier accumulators to the memory, by use of n number of channels, and not to transfer the dummy output data from the at least one or more of the n number of multiplier accumulators to the memory, wherein the at least one or more of the n number of multiplier accumulators perform the dummy calculation in a period from a timing at which the second output-side DMA controller ends data transfer to the memory to a timing at which the second input-side DMA controller starts data transfer from the memory. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a sequence controller configured to output a read start signal for starting the data transfer from the memory to the second input-side DMA controller, wherein the second output-side DMA controller outputs a write end signal when ending the data transfer to the memory, and wherein the dummy circuit outputs the dummy data to the at least one or more of multiplier accumulators in response to the write end signal from the second output-side DMA controller, and outputs the respective pieces of input data from the second input-side DMA controller to the n number of multiplier accumulators in response to the read start signal from the sequence controller. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, the sequence controller further divides the n number of channels of each of the second input-side DMA controller and the second output-side DMA controller and the n number of multiplier accumulators into m (m is an integer smaller than n) number of groups, and outputs, to the second input-side DMA controller, the read start signal for each of the m number of groups at different timings from one another, thereby controlling such that a series of operation timings including a read operation by the second input-side DMA controller, a calculation operation by the multiplier accumulator, and a write operation by the second output-side DMA controller is different from one another among the m number of groups, wherein the second output-side DMA controller outputs the write end signal to each of the m number of groups, and wherein the dummy circuit causes the multiplier accumulator of each of the m number of groups to perform the dummy calculation, according to the write end signal for each of the m number of groups and the read start signal for each of the m number of groups. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the dummy circuit causes part of the m number of groups to perform the dummy calculation. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the part of the m number of groups is allowed to be changed by setting. ### Claim 6 (depends on 3) The semiconductor device according to claim 3, wherein the m number of groups are allowed to be changed by setting. ### Claim 7 A semiconductor device that executes neural network processing, comprising: n (n is an integer that is two or more) number of multiplier accumulators configured to multiply and accumulate pieces of input data and parameters; one or a plurality of memories configured to store the pieces of input data and the parameters; a first DMA (Direct Memory Access) controller configured to transfer the parameters stored in the memory to the n number of multiplier accumulators; a second input-side DMA controller configured to transfer the pieces of input data stored in the memory to the n number of multiplier accumulators, by use of n number of channels, respectively, and cause the n number of multiplier accumulators to perform calculations and to thereby output corresponding pieces of normal output data serving as the calculation results; a dummy circuit configured to output dummy data determined in advance to at least one or more of the n number of multiplier accumulators, thereby causing the at least one or more of the n number of multiplier accumulators to perform a dummy calculation and to output dummy output data serving as the dummy calculation result; a second output-side DMA controller configured to transfer the respective pieces of normal output data from the n number of multiplier accumulators to the memory, by use of n number of channels, and not to transfer the dummy output data from the at least one or more of the n number of multiplier accumulators to the memory; and a sequence controller configured to output a read start signal for starting the data transfer from the memory to the second input-side DMA controller, wherein the sequence controller divides the n number of channels of each of the second input-side DMA controller and the second output-side DMA controller and the n number of multiplier accumulators into m (m is an integer smaller than n) number of groups, and outputs, to the second input-side DMA controller, the read start signal for each of the m number of groups at different timings from one another, thereby controlling such that a series of operation timings including a read operation by the second input-side DMA controller, a calculation operation by the multiplier accumulator, and a write operation by the second output-side DMA controller is different from one another among the m number of groups. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the m number of groups are allowed to be changed by setting. ### Claim 9 A semiconductor device including one semiconductor chip, comprising: a neural network engine configured to execute neural network processing; one or a plurality of memories configured to store pieces of input data and parameters; a processor; and a bus configured to connect the neural network engine, the memories, and the processor with each other, wherein the neural network engine includes: n (n is an integer that is two or more) number of multiplier accumulators configured to multiply and accumulate pieces of input data and parameters; one or a plurality of memories configured to store the pieces of input data and the parameters; a first DMA (Direct Memory Access) controller configured to transfer the parameters stored in the memory to the n number of multiplier accumulators; a second input-side DMA controller configured to transfer the pieces of input data stored in the memory to the n number of multiplier accumulators, by use of n number of channels, respectively, and cause the n number of multiplier accumulators to perform calculations and to thereby output corresponding pieces of normal output data serving as the calculation results; a dummy circuit configured to output dummy data determined in advance to at least one or more of the n number of multiplier accumulators, thereby causing the at least one or more of the n number of multiplier accumulators to perform a dummy calculation and to output dummy output data serving as the dummy calculation result; and a second output-side DMA controller configured to transfer the respective pieces of normal output data from the n number of multiplier accumulators to the memory, by use of n number of channels, and not to transfer the dummy output data from the at least one or more of the n number of multiplier accumulators to the memory, wherein the at least one or more of the n number of multiplier accumulators perform the dummy calculation in a period from a timing at which the second output-side DMA controller ends data transfer to the memory to a timing at which the second input-side DMA controller starts data transfer from the memory. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the neural network engine further includes a sequence controller configured to output a read start signal for starting the data transfer from the memory to the second input-side DMA controller, wherein the second output-side DMA controller outputs a write end signal when ending the data transfer to the memory, and wherein the dummy circuit outputs the dummy data to the at least one or more of multiplier accumulators in response to the write end signal from the second output-side DMA controller, and outputs the respective pieces of input data from the second input-side DMA controller to the n number of multiplier accumulators in response to the read start signal from the sequence controller. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, the sequence controller further divides the n number of channels of each of the second input-side DMA controller and the second output-side DMA controller and the n number of multiplier accumulators into m (m is an integer smaller than n) number of groups, and outputs, to the second input-side DMA controller, the read start signal for each of the m number of groups at different timings from one another, thereby controlling such that a series of operation timings including a read operation by the second input-side DMA controller, a calculation operation by the multiplier accumulator, and a write operation by the second output-side DMA controller is different from one another among the m number of groups, wherein the second output-side DMA controller outputs the write end signal to each of the m number of groups, and wherein the dummy circuit causes the multiplier accumulator of each of the m number of groups to perform the dummy calculation, according to the write end signal for each of the m number of groups and the read start signal for each of the m number of groups. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the dummy circuit causes part of the m number of groups to perform the dummy calculation.