# US 12,182,038 B2 · Methods and apparatus for allocation in a victim cache system

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- Number: US 12,182,038 B2
- Document ID: US12182038B2
- Status: Granted
- Kind: B2
- Application number: 18/406,319
- Filed: 2024-01-08
- Published: 2024-05-02
- Granted: 2024-12-31
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Bhoria; Timothy David Anderson; Pete Michael Hippleheuser
- Web page: https://patentgrep.com/patent/US12182038B2

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

## Claims

### Claim 1

A device comprising:
a processor core; and
a cache system coupled to the processor core that includes:
a first cache control circuit configured to receive a read operation;
a first cache storage coupled to the first cache control circuit, wherein the first cache storage has a first type of associativity;
a first tag memory coupled to the first cache control circuit and configured to store a first set of tags associated with the first cache storage;
a second cache control circuit configured to receive the read operation in parallel with the first cache control circuit;
a second cache storage coupled to the second cache control circuit, wherein the second cache storage has a second type of associativity that is different from the first type of associativity; and
a second tag memory coupled to the second cache control circuit and configured to store a second set of tags associated with the second cache storage.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the first cache control circuit is configured to determine, using the first tag memory, whether the read operation is associated with a read-miss in the first cache storage; and
the second cache control circuit is configured to determine, using the second tag memory, whether the read operation is associated with a read-miss in the second cache storage, in parallel with the first cache control circuit determining whether the read operation is associated with a read-miss in the first cache storage.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first cache control circuit is configured to:
determine whether the read operation is associated with a read-miss in the first cache storage; and
based on the read operation being associated with the read-miss in the first cache storage, cause a set of data to be written from the first cache storage to the second cache storage.

### Claim 4 (depends on 3)

The device of claim 3, wherein the first cache control circuit is configured to cause the set of data to be written from the first cache storage to the second cache storage regardless of whether the first tag memory specifies that the set of data is clean or dirty.

### Claim 5 (depends on 3)

The device of claim 3, wherein:
the set of data is a first set of data; and
the second cache control circuit is configured to, based on the read operation being associated with a hit in the second cache storage, provide a second set of data from the second cache storage as a response to the read operation.

### Claim 6 (depends on 5)

The device of claim 5, wherein the second cache control circuit is configured to, based on the read operation being associated with a hit in the second cache storage, cause the second set of data to be written from the second cache storage to the first cache storage.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first cache storage is direct mapped and the second cache storage is fully associative.

### Claim 8 (depends on 1)

The device of claim 1, wherein:
the cache system is a first cache system;
the device further comprises a second cache system coupled to the first cache system; and
the first cache system is configured to provide the read operation to the second cache system based on the read operation being associated with a read-miss in the first cache storage and a read-miss in the second cache storage.

### Claim 9 (depends on 8)

The device of claim 8, wherein:
the first cache system is a level-one (L1) cache system; and
the second cache system is a level-two (L2) cache system.

### Claim 10 (depends on 1)

The device of claim 1, wherein:
the cache system is a level-one (L1) cache system;
the first cache storage is an L1 main cache storage; and
the second cache storage is an L1 victim cache storage.

### Claim 11 (depends on 1)

The device of claim 1, wherein the processor core is configured to provide the read operation to the cache system.

### Claim 12

A device comprising:
a cache system that includes:
a cache control circuit configured to receive a read operation;
a first cache storage coupled to the cache control circuit, wherein the first cache storage has a first type of associativity;
a first tag memory coupled to the cache control circuit and configured to store a first set of tags associated with the first cache storage;
a second cache storage coupled to the cache control circuit, wherein the second cache storage has a second type of associativity that is different from the first type of associativity; and
a second tag memory coupled to the cache control circuit and configured to store a second set of tags associated with the second cache storage.

### Claim 13 (depends on 12)

The device of claim 12, wherein, the cache control circuit is configured to determine, in parallel:
whether the read operation is associated with a read-miss in the first cache storage using the first tag memory; and
whether the read operation is associated with a read-miss in the second cache storage using the second tag memory.

### Claim 14 (depends on 12)

The device of claim 12, wherein the cache control circuit is configured to:
determine whether the read operation is associated with a read-miss in the first cache storage; and
based on the read operation being associated with the read-miss in the first cache storage, cause a set of data to be written from the first cache storage to the second cache storage.

### Claim 15 (depends on 14)

The device of claim 14, wherein the cache control circuit is configured to cause the set of data to be written from the first cache storage to the second cache storage regardless of whether the first tag memory specifies that the set of data is clean or dirty.

### Claim 16 (depends on 14)

The device of claim 14, wherein:
the set of data is a first set of data; and
the cache control circuit is configured to, based on the read operation being associated with a hit in the second cache storage, provide a second set of data from the second cache storage as a response to the read operation.

### Claim 17 (depends on 16)

The device of claim 16, wherein the cache control circuit is configured to, based on the read operation being associated with a hit in the second cache storage, cause the second set of data to be written from the second cache storage to the first cache storage.

### Claim 18 (depends on 12)

The device of claim 12, wherein the first cache storage is direct mapped and the second cache storage is fully associative.

### Claim 19 (depends on 12)

The device of claim 12, wherein:
the cache system is a level-one (L1) cache system;
the first cache storage is an L1 main cache storage; and
the second cache storage is an L1 victim cache storage.

### Claim 20 (depends on 12)

The device of claim 12 further comprising a processor core coupled to the cache control circuit and configured to provide the read operation to the cache system.