# US 12,182,033 B2 · Address translation cache and system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,033 B2 - Document ID: US12182033B2 - Status: Granted - Kind: B2 - Application number: 17/965,700 - Filed: 2022-10-13 - Published: 2023-06-01 - Granted: 2024-12-31 - Earliest claimed: 2021-12-01 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Youngsuk Moon; Hyunwoo Kang; Jaegeun Park; Sangmuk Hwang - Web page: https://patentgrep.com/patent/US12182033B2 ## CPC - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA] - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 12/1045: associated with a data cache - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/404: {with address mapping} - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F 2212/1016: Performance improvement - G06F 2212/1044: Space efficiency improvement - G06F 2212/652: Page size control - G06F 2212/657: Virtual address space management - G06F 2212/681: Multi-level TLB, e.g. microTLB and main TLB - G06F 2212/683: Invalidation - G06F 2213/28: DMA - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information. ## Claims ### Claim 1 An address translation cache (ATC) configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device, the ATC comprising: a plurality of flexible page group caches, each flexible page group cache configured to store translation entries corresponding to a page size allocated to the flexible page group cache; a shared cache configured to store, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches; and a cache manager configured to allocate a page size to each flexible page group cache, manage cache page information on the page sizes allocated to the plurality of flexible page group caches, and control the plurality of flexible page group caches and the shared cache based on the cache page information, wherein the plurality of flexible page group caches are implemented with a plurality of set associative caches and the shared cache is implemented with a fully associative cache. ### Claim 2 (depends on 1) The ATC of claim 1, wherein the cache manager is configured such that when the cache manager receives an input translation entry corresponding to the page size that is identical to one of the page sizes allocated to the plurality of flexible page group caches, the cache manager stores the input translation entry in the flexible page group cache to which the page size corresponding to the input translation entry is allocated. ### Claim 3 (depends on 1) The ATC of claim 1, wherein the cache manager is further configured such that when the cache manager receives an input translation entry corresponding to a new page size that is different from the page sizes allocated to the plurality of flexible page group caches and there exists an empty flexible page group cache among the plurality of flexible page group caches to which the page size is not allocated, the cache manager allocates the new page size to the empty flexible page group cache and stores the input translation entry in the empty flexible page group cache to which the new page size is allocated. ### Claim 4 (depends on 1) The ATC of claim 1, wherein the cache manager is configured to store, in the shared cache, a translation entry evicted from the plurality of flexible page group caches. ### Claim 5 (depends on 1) The ATC of claim 1, wherein the plurality of set associative caches each include the same number of sets. ### Claim 6 (depends on 5) The ATC of claim 5, wherein each translation entry in each set associative cache includes a tag, and a number of bits of each tag stored in each set associative cache is decreased as the page size allocated to each set associative cache is increased. ### Claim 7 (depends on 1) The ATC of claim 1, wherein the cache manager is configured such that for each virtual address input to the ATC, when the cache manager searches for a physical address mapped to the input virtual address, the cache manager searches all of the plurality of set associative caches and the fully associative cache. ### Claim 8 (depends on 7) The ATC of claim 7, wherein the cache manager is configured to extract, from the input virtual addresses, tags and indexes corresponding to the page sizes allocated to the plurality of set associative caches based on the cache page information, and provide the tags and indexes respectively to the corresponding set associative caches. ### Claim 9 (depends on 1) The ATC of claim 1, wherein the cache manager is configured such that, when the cache manager invalidates a translation entry corresponding to an input virtual address, the cache manager searches all of the plurality of set associative caches and the fully associative cache. ### Claim 10 (depends on 1) The ATC of claim 1, further comprising: a plurality of function-dedicated caches dedicated to a plurality of functions, each function-dedicated cache configured to store translation entries related to each function. ### Claim 11 (depends on 10) The ATC of claim 10, wherein the plurality of function-dedicated caches correspond to a lower-level cache group and the plurality of flexible page group caches and the shared cache correspond to a higher-level cache group. ### Claim 12 (depends on 10) The ATC of claim 10, wherein the cache manager is configured such that when the cache manager searches for a physical address mapped to an input virtual address, the cache manager searches the function-dedicated cache corresponding to a function identifier included in the input virtual address and searches all of the plurality of flexible page group caches and the shared cache when the translation entry corresponding to the input virtual address does not exist in the function-dedicated cache corresponding to the function identifier. ### Claim 13 (depends on 10) The ATC of claim 10, wherein the cache manager is configured such that when the cache manager invalidates a translation entry corresponding to an input virtual address, the cache manager searches all of the plurality of function-dedicated caches, the plurality of flexible page group caches and the shared cache. ### Claim 14 (depends on 10) The ATC of claim 10, wherein the cache manager is configured to store, in the plurality of flexible page group caches or the shared cache, a translation entry evicted from the plurality of function-dedicated caches. ### Claim 15 (depends on 10) The ATC of claim 10, wherein the plurality of function-dedicated caches are implemented with a plurality of fully associative caches. ### Claim 16 (depends on 10) The ATC of claim 10, wherein the plurality of functions are functions according to a peripheral component interconnect express (PCIe) standard. ### Claim 17 An address translation cache (ATC) configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device, the ATC comprising: a plurality of flexible page group caches, each flexible page group cache configured to store translation entries corresponding to a page size allocated to the flexible page group cache; a shared cache configured to store, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches; a cache manager configured to allocate a page size to each flexible page group cache, manage cache page information on the page sizes allocated to the plurality of flexible page group caches, and control the plurality of flexible page group caches and the shared cache based on the cache page information, wherein the cache manager is further configured such that: when the cache manager receives an input translation entry corresponding to a new page size that is different from the page sizes allocated to the plurality of flexible page group caches and there exists an empty flexible page group cache among the plurality of flexible page group caches to which the page size is not allocated, the cache manager allocates the new page size to the empty flexible page group cache and stores the input translation entry in the empty flexible page group cache to which the new page size is allocated, and when the cache manager receives an input translation entry corresponding to a new page size that is different from the page sizes allocated to the plurality of flexible page group caches and there does not exist an empty flexible page group cache to which the page size is not allocated, the cache manager stores the input translation entry in the shared cache. ### Claim 18 (depends on 17) The ATC of claim 17, wherein the plurality of flexible page group caches are implemented with a plurality of set associative caches and the shared cache is implemented with a fully associative cache. ### Claim 19 A system comprising: a host memory device; a host processor; a direct memory access device configured to perform a direct memory access to the host memory device, the direct memory access device including an address translation cache (ATC) configured to store translation entries indicating mapping information between a virtual address of the host processor and a physical address of a memory device; and a memory management unit configured to manage access of the host processor and the direct memory access device to the host memory device, wherein the ATC includes: a plurality of flexible page group caches, each flexible page group cache configured to store translation entries corresponding to a page size allocated to the flexible group cache; a shared cache configured to store, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches; and a cache manager configured to allocate the page size to each flexible page group cache, manage cache page information on the page sizes allocated to the plurality of flexible page group caches, and control the plurality of flexible page group caches and the shared cache based on the cache page information, wherein the plurality of flexible page group caches are implemented with a plurality of set associative caches and the shared cache is implemented with a fully associative cache. ### Claim 20 An address translation cache (ATC) configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device, the ATC comprising: a plurality of function-dedicated caches dedicated to a plurality of functions and implemented with a plurality of fully associative caches, each function-dedicated cache configured to store translation entries related to a respective function; a plurality of flexible page group caches implemented with a plurality of set associative caches, each flexible page group cache configured to store translation entries corresponding to a page size allocated to the flexible group cache and not stored in the plurality of function-dedicated caches; a shared cache implemented with a fully associative cache, the shared cache configured to store, regardless of page sizes, translation entries that are not stored in the plurality of function-dedicated caches or the plurality of flexible page group caches; and a cache manager configured to allocate the page size to each flexible page group cache, manage cache page information on the page sizes allocated to the plurality of flexible page group caches, and control the plurality of flexible page group caches and the shared cache based on the cache page information.