# US 12,182,026 B1 · Computer processor architecture for coalescing of atomic operations

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- Number: US 12,182,026 B1
- Document ID: US12182026B1
- Status: Granted
- Kind: B1
- Application number: 18/342,509
- Filed: 2023-06-27
- Published: 2025-01-02
- Granted: 2024-12-31
- Earliest claimed: 2023-06-27
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Jedd O. Haberstro; Mladen Wilder
- Web page: https://patentgrep.com/patent/US12182026B1

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F 12/0815: Cache consistency protocols
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0857: {by multiple requestors}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F 2212/1028: Power efficiency
- G06F 2212/455: Image or video data
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques are disclosed relating to smashing atomic operations. In some embodiments, cache control circuitry caches data values in cache storage circuitry and receive multiple requests to atomically update a cached data value according to one or more arithmetic operations. The control circuitry may perform updates to a cached data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria and store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value. The control circuitry may, in response to an event, flush, to a higher level in a memory hierarchy that includes the cache storage circuitry both: the updated data value and the operation information. This may advantageously smash atomic operations at the cache and reduce operations to the higher-level cache or memory (which may be the actual coherence point for atomic requests).

## Claims

### Claim 1

An apparatus, comprising:
cache storage circuitry;
cache control circuitry configured to:
cache data values in the cache storage circuitry;
receive multiple requests to atomically update a cached data value according to one or more arithmetic operations;
perform updates to a cached data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria;
store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value; and
in response to an event, flush, to a higher level in a memory hierarchy that includes the cache storage circuitry:
the updated data value; and
the operation information.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the cache control circuitry includes arithmetic logic unit circuitry configured to perform the arithmetic operations.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the event is a first request with a first arithmetic operation that does not meet the one or more criteria; and
the cache control circuitry is further configured to, subsequent to the flush:
store, based on the first arithmetic operation, data in the cache storage circuitry for the first request; and
update the operation information to reflect the first arithmetic operation.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the higher level in the memory hierarchy is a coherence point for the requests to atomically update the cached data value; and
the higher level in the memory hierarchy includes circuitry configured to perform the operation indicated by the flushed operation information on input values that include the updated data value and a data value stored in the higher level in the memory hierarchy.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the cache control circuitry is configured to store metadata that includes the operation information in a cache line with the corresponding updated data value.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the metadata further indicates:
whether one or more values in the cache line correspond to atomic operations;
one or more data types for one or more values in the cache line that correspond to atomic operations; and
valid indicators for different portions of the cache line.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the cache control circuitry is configured to maintain the metadata at cache line granularity.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the event is a cache eviction or a cache maintenance operation.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the cache control circuitry is configured to perform the updates for atomic operations that do not request a return value.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein at least some of the multiple requests are from different single-instruction multiple-data (SIMD) groups.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein at least some of the multiple requests are from different threadgroups corresponding to different programs.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the one or more criteria include:
one or more relationships between a current arithmetic operation and the most-recent requested atomic arithmetic operation; and
one or more relationships between data types.

### Claim 13

A method, comprising:
caching, by a computing system, data values in cache storage;
receiving, by the computing system, multiple requests to atomically update a cached data value according to one or more arithmetic operations;
performing, by the computing system, updates to a cached data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria;
storing, by the computing system, store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value; and
in response to an event, the computing system flushing, to a higher level in a memory hierarchy that includes the cache storage:
the updated data value; and
the operation information.

### Claim 14 (depends on 13)

The method of claim 13, wherein the event is a first request with a first arithmetic operation that does not meet the one or more criteria, the method further comprising, subsequent to the flush:
storing, by the computing system based on the first arithmetic operation, data in the cache storage for the first request; and
updating, by the computing system, the operation information to reflect the first arithmetic operation.

### Claim 15 (depends on 13)

The method of claim 13, wherein the higher level in the memory hierarchy is a coherence point for the requests to atomically update the cached data value, the method further comprising the higher level in the memory hierarchy includes circuitry performing the operation indicated by the flushed operation information on input values that include the updated data value and a data value stored in the higher level in the memory hierarchy.

### Claim 16 (depends on 13)

The method of claim 13, wherein at least some of the multiple requests are from different threadgroups corresponding to different programs.

### Claim 17 (depends on 13)

The method of claim 13, wherein the one or more criteria include:
one or more relationships between a current arithmetic operation and the most-recent requested atomic arithmetic operation; and
one or more relationships between data types.

### Claim 18

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:
cache storage circuitry;
cache control circuitry configured to:
cache data values in the cache storage circuitry;
receive multiple requests to atomically update a cached data value according to one or more arithmetic operations;
perform updates to a cached data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria;
store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value; and
in response to an event, flush, to a higher level in a memory hierarchy that includes the cache storage circuitry:
the updated data value; and
the operation information.

### Claim 19 (depends on 18)

The non-transitory computer-readable medium of claim 18, wherein:
the event is a first request with a first arithmetic operation that does not meet the one or more criteria; and
the cache control circuitry is further configured to, subsequent to the flush:
store, based on the first arithmetic operation, data in the cache storage circuitry for the first request; and
update the operation information to reflect the first arithmetic operation.

### Claim 20 (depends on 18)

The non-transitory computer-readable medium of claim 18, wherein at least some of the multiple requests are from different threadgroups corresponding to different programs.