# US 12,182,025 B2 · Flexible cache allocation technology priority-based cache line eviction algorithm

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- Number: US 12,182,025 B2
- Document ID: US12182025B2
- Status: Granted
- Kind: B2
- Application number: 18/321,603
- Filed: 2023-05-22
- Published: 2023-12-21
- Granted: 2024-12-31
- Earliest claimed: 2019-11-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Neha Gholkar; Akhilesh Kumar
- Web page: https://patentgrep.com/patent/US12182025B2

## CPC

- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/121: using replacement algorithms
- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/60: Details of cache memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

## Claims

### Claim 1

A processor comprising:
a plurality of cores;
an N-way set associative cache where N is an integer greater than one; and
a cache control circuit coupled with the N-way set associative cache, the cache control circuit to:
receive a cache fill request for an incoming cache line corresponding to an application;
select a victim cache line in the N-way set associative cache based at least in part on a maximum occupancy bound specified for the application and a current occupancy in the N-way set associative cache for the application, wherein the maximum occupancy bound corresponds to a maximum number of ways per set to be used by the application, and wherein the current occupancy is a number of ways currently used by the application in a set indexed by the incoming cache line; and
store the incoming cache line to a location of the selected victim cache line.

### Claim 2 (depends on 1)

The processor of claim 1, wherein, if the current occupancy is at or above the maximum occupancy bound, the cache control circuit is to select a cache line currently used by the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the cache control circuit is to select the victim cache line based at least in part on a minimum occupancy bound specified for the application.

### Claim 4 (depends on 3)

The processor of claim 3, wherein, if the current occupancy is less than the minimum occupancy bound, the cache control circuit is to select a cache line having a priority lower than a priority corresponding to the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 5 (depends on 3)

The processor of claim 3, wherein the minimum occupancy bound is to be specified in a register.

### Claim 6 (depends on 1)

The processor of claim 1, wherein, to select the victim cache line, the cache control circuit is to dynamically select a way based at least in part on the current occupancy.

### Claim 7 (depends on 1)

The processor of claim 1, wherein, if an invalid cache line exists in the set indexed by the incoming cache line, the cache control circuit is to select the invalid cache line as the victim cache line.

### Claim 8 (depends on 1)

The processor of claim 1, further comprising a cache monitor circuit to monitor use of the N-way set associative cache.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the cache monitor circuit is to adjust the maximum occupancy bound.

### Claim 10

An apparatus comprising:
a memory controller; and
a processor coupled with the memory controller, the processor comprising:
a plurality of cores;
a N-way set associative cache where N is an integer greater than one; and
a cache control circuit coupled with the N-way set associative cache, the cache control circuit to:
receive a cache fill request for an incoming cache line corresponding to an application;
select a victim cache line in the N-way set associative cache based at least in part on a maximum occupancy bound specified for the application and a current occupancy in the N-way set associative cache for the application, wherein the maximum occupancy bound corresponds to a maximum number of ways per set to be used by the application, and wherein the current occupancy is a number of ways currently used by the application in a set indexed by the incoming cache line; and
store the incoming cache line to a location of the selected victim cache line.

### Claim 11 (depends on 10)

The apparatus of claim 10, further comprising a graphics processing unit coupled with the processor, and wherein, if the current occupancy is at or above the maximum occupancy bound, the cache control circuit is to select a cache line currently used by the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 12 (depends on 10)

The apparatus of claim 10, further comprising a coprocessor coupled with the processor, and wherein the cache control circuit is to select the victim cache line based at least in part on a minimum occupancy bound specified for the application.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising a display unit coupled with the processor, and wherein, if the current occupancy is less than the minimum occupancy bound, the cache control circuit is to select a cache line having a priority lower than a priority corresponding to the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 14 (depends on 10)

The apparatus of claim 10, further comprising an image processor coupled with the processor, and wherein, to select the victim cache line, the cache control circuit is to dynamically select a way based at least in part on the current occupancy.

### Claim 15

A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
a plurality of cores;
an N-way set associative cache where N is an integer greater than one; and
a cache control circuit coupled with the N-way set associative cache, the cache control circuit to:
receive a cache fill request for an incoming cache line corresponding to an application;
select a victim cache line in the N-way set associative cache based at least in part on a maximum occupancy bound specified for the application and a current occupancy in the N-way set associative cache for the application, wherein the maximum occupancy bound corresponds to a maximum number of ways per set to be used by the application, and wherein the current occupancy is a number of ways currently used by the application in a set indexed by the incoming cache line; and
store the incoming cache line to a location of the selected victim cache line.

### Claim 16 (depends on 15)

The system of claim 15, wherein the system memory is a dynamic random access memory (DRAM), and wherein, if the current occupancy is at or above the maximum occupancy bound, the cache control circuit is to select a cache line currently used by the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 17 (depends on 15)

The system of claim 15, further comprising a mass storage device coupled with the processor, and wherein the cache control circuit is to select the victim cache line based at least in part on a minimum occupancy bound specified for the application.

### Claim 18 (depends on 17)

The system of claim 17, further comprising a coprocessor coupled with the processor, and wherein, if the current occupancy is less than the minimum occupancy bound, the cache control circuit is to select a cache line having a priority lower than a priority corresponding to the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 19 (depends on 15)

The system of claim 15, further comprising a communication device coupled with the processor, and wherein, to select the victim cache line, the cache control circuit is to dynamically select a way based at least in part on the current occupancy.

### Claim 20

A method comprising:
processing data with a plurality of cores;
storing data in an N-way set associative cache where N is an integer greater than one;
receiving, at a cache control circuit, a cache fill request for an incoming cache line corresponding to an application;
selecting, with the cache control circuit, a victim cache line in the N-way set associative cache based at least in part on a maximum occupancy bound specified for the application and a current occupancy in the N-way set associative cache for the application, wherein the maximum occupancy bound corresponds to a maximum number of ways per set to be used by the application, and wherein the current occupancy is a number of ways currently used by the application in a set indexed by the incoming cache line; and
storing the incoming cache line to a location of the selected victim cache line.

### Claim 21 (depends on 20)

The method of claim 20, wherein, if the current occupancy is at or above the maximum occupancy bound, the cache control circuit is to select a cache line currently used by the application in the set indexed by the incoming cache line, as the victim cache line.

### Claim 22 (depends on 20)

The method of claim 20, wherein selecting the victim cache line is also based at least in part on a minimum occupancy bound specified for the application.

### Claim 23 (depends on 22)

The method of claim 22, wherein, if the current occupancy is less than the minimum occupancy bound, the cache control circuit selects a cache line having a priority lower than a priority corresponding to the application in the set indexed by the incoming cache line, as the victim cache line.