# US 12,182,023 B2 · Opportunistic late depth testing to prevent stalling for overlapping cache lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,023 B2 - Document ID: US12182023B2 - Status: Granted - Kind: B2 - Application number: 17/355,856 - Filed: 2021-06-23 - Published: 2022-12-29 - Granted: 2024-12-31 - Earliest claimed: 2021-06-23 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Saikat Mandal; Eric Hoekstra; Vasanth Ranganathan; Prasoonkumar Surti - Web page: https://patentgrep.com/patent/US12182023B2 ## CPC - G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) - G06T 1/60: Memory management - G06F 12/0815: Cache consistency protocols - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06T 7/50: Depth or shape recovery - G06F 2212/1024: Latency reduction - G06F 2212/455: Image or video data - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Methods, systems and apparatuses provide for graphics processor technology that determines whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing, and when the first cache line overlaps the second cache line, switches the first cache line to be allocated for late depth testing, and bypasses an early depth test for the first cache line. The technology can also compare coordinates of the first cache line with the coordinates of the second cache line, where an overlap is determined when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. Additionally, the technology can also perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any existing cache lines allocated for late depth testing. ## Claims ### Claim 1 A computing system comprising: a network controller; and a graphics processor coupled to the network controller, wherein the graphics processor includes logic coupled to one or more substrates, the logic to: determine whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing; and when the first cache line overlaps the second cache line: switch the first cache line to be allocated for late depth testing; and bypass an early depth test for the first cache line. ### Claim 2 (depends on 1) The computing system of claim 1, wherein the logic is further to store coordinates of the second cache line in a buffer. ### Claim 3 (depends on 2) The computing system of claim 2, wherein to determine whether the first cache line overlaps the second cache line comprises to compare coordinates of the first cache line with the coordinates of the second cache line. ### Claim 4 (depends on 3) The computing system of claim 3, wherein an overlap is determined between the first cache line and the second cache line when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. ### Claim 5 (depends on 2) The computing system of claim 2, wherein the first cache line and the second cache line are aligned, and wherein an overlap is determined between the first cache line and the second cache line when coordinates for an initial pixel in the first cache line match coordinates for an initial pixel in the second cache line. ### Claim 6 (depends on 2) The computing system of claim 2, wherein the logic is to perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any cache line allocated for late depth testing. ### Claim 7 A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, the logic implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic to: determine whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing; and when the first cache line overlaps the second cache line: switch the first cache line to be allocated for late depth testing; and bypass an early depth test for the first cache line. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the logic is further to store coordinates of the second cache line in a buffer. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein to determine whether the first cache line overlaps the second cache line comprises to compare coordinates of the first cache line with the coordinates of the second cache line. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein an overlap is determined between the first cache line and the second cache line when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the first cache line and the second cache line are aligned, and wherein an overlap is determined between the first cache line and the second cache line when coordinates for an initial pixel in the first cache line match coordinates for an initial pixel in the second cache line. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the logic is to perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any cache line allocated for late depth testing. ### Claim 13 At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a graphics apparatus, cause the graphics apparatus to: determine whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing; and when the first cache line overlaps the second cache line: switch the first cache line to be allocated for late depth testing; and bypass an early depth test for the first cache line. ### Claim 14 (depends on 13) The at least one non-transitory computer readable storage medium of claim 13, wherein the instructions, when executed, further cause the graphics apparatus to store coordinates of the second cache line in a buffer. ### Claim 15 (depends on 14) The at least one non-transitory computer readable storage medium of claim 14, wherein to determine whether the first cache line overlaps the second cache line comprises to compare coordinates of the first cache line with the coordinates of the second cache line. ### Claim 16 (depends on 15) The at least one non-transitory computer readable storage medium of claim 15, wherein an overlap is determined between the first cache line and the second cache line when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. ### Claim 17 (depends on 14) The at least one non-transitory computer readable storage medium of claim 14, wherein the first cache line and the second cache line are aligned, and wherein an overlap is determined between the first cache line and the second cache line when coordinates for an initial pixel in the first cache line match coordinates for an initial pixel in the second cache line. ### Claim 18 (depends on 14) The at least one non-transitory computer readable storage medium of claim 14, wherein the instructions, when executed, further cause the graphics apparatus to perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any cache line allocated for late depth testing. ### Claim 19 A method comprising: determining whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing; and when the first cache line overlaps the second cache line: switching the first cache line to be allocated for late depth testing; and bypassing an early depth test for the first cache line. ### Claim 20 (depends on 19) The method of claim 19, further comprising storing coordinates of the second cache line in a buffer. ### Claim 21 (depends on 20) The method of claim 20, wherein determining whether the first cache line overlaps the second cache line comprises comparing coordinates of the first cache line with the coordinates of the second cache line. ### Claim 22 (depends on 21) The method of claim 21, wherein an overlap is determined between the first cache line and the second cache line when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. ### Claim 23 (depends on 20) The method of claim 20, wherein the first cache line and the second cache line are aligned, and wherein an overlap is determined between the first cache line and the second cache line when coordinates for an initial pixel in the first cache line match coordinates for an initial pixel in the second cache line. ### Claim 24 (depends on 20) The method of claim 20, further comprising performing early depth testing on each pixel in the first cache line when the first cache line does not overlap any cache line allocated for late depth testing.