# US 12,182,019 B2 · Microprocessor that prevents same address load-load ordering violations using physical address proxies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,182,019 B2 - Document ID: US12182019B2 - Status: Granted - Kind: B2 - Application number: 17/747,784 - Filed: 2022-05-18 - Published: 2022-11-10 - Granted: 2024-12-31 - Earliest claimed: 2021-05-07 - Assignees: Ventana Micro Systems Inc. - Applicants: Ventana Micro Systems Inc. - Inventors: John G. Favor; Srivatsan Srinivasan - Web page: https://patentgrep.com/patent/US12182019B2 ## CPC - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)} - G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 12/1045: associated with a data cache - G06F 12/1063: {the data cache being concurrently virtually addressed} - G06F 2212/1024: Latency reduction - G06F 2212/27: Using a specific cache architecture - G06F 2212/452: Instruction code - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A L2 set associative cache that is inclusive of an L1 cache. Each entry of a load queue holds a load physical address proxy (PAP) for a load physical memory line address (PMLA) rather than the load PMLA itself. The load PAP comprises the set index and the way that uniquely identifies the L2 entry that holds a memory line specified by the load PMLA. Each load queue entry indicates whether the load instruction has completed execution. The microprocessor removes a memory line at a removal PMLA from an L2 entry and forms a removal PAP as a proxy for the removal PMLA. The removal PAP comprises a set index and a way that uniquely identifies the removed entry. The microprocessor snoops the load queue with the removal PAP to determine whether the removal PAP matches one or more load PAPs in one or more load queue entries associated with one or more load instructions that have completed execution and, if so, signals an abort request. ## Claims ### Claim 1 A microprocessor, comprising: a first-level cache and a second-level set associative cache that is inclusive of the first-level cache, wherein each entry of the second-level cache is uniquely identified by a set index and a way; a load queue, wherein each entry of the load queue is configured to hold: a load physical address proxy (PAP) for a load physical memory line address associated with a load instruction rather than holding the load physical memory line address itself, wherein the load PAP comprises the set index and the way that uniquely identifies the entry of the second-level cache that holds a copy of a line of memory specified by the load physical memory line address; and an indication of whether the load instruction has completed execution; wherein the microprocessor is configured to: perform a removal of a copy of a line of memory at a removal physical memory line address from an entry of the second-level cache; form a removal PAP as a proxy for the removal physical memory line address, wherein the removal PAP comprises a set index and a way that uniquely identifies the removed entry; perform a snoop of the load queue with the removal PAP; and determine, based on the snoop, whether a condition is true, wherein the condition comprises: the removal PAP matches one or more load PAPs in one or more entries of the load queue associated with one or more load instructions that have completed execution; and if the condition is true, signal an abort request. ### Claim 2 (depends on 1) The microprocessor of claim 1, wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions. ### Claim 3 (depends on 1) The microprocessor of claim 1, further comprising: a load unit; wherein a load instruction has completed execution when the load unit has written a load PAP to an entry of the load queue associated with the load instruction. ### Claim 4 (depends on 3) The microprocessor of claim 3, wherein each valid entry of the first-level cache holds a PAP of a physical memory line address of a cache line stored in the valid entry; and wherein the load unit is further configured to, during execution of the load instruction, receive a PAP from the first-level cache and write the PAP to the entry of the load queue associated with the load instruction and set the indication that the load instruction has completed execution. ### Claim 5 (depends on 1) The microprocessor of claim 1, wherein in response to the abort request, the microprocessor is further configured to determine a flush boundary and flush at least all load instructions younger than the flush boundary. ### Claim 6 (depends on 5) The microprocessor of claim 5, wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has not completed execution. ### Claim 7 (depends on 6) The microprocessor of claim 6, wherein in response to the abort request, the microprocessor is further configured to block dispatch of load instructions until all load instructions older than the flush boundary have committed. ### Claim 8 (depends on 5) The microprocessor of claim 5, wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has completed execution and whose load PAP matches the removal PAP. ### Claim 9 (depends on 1) The microprocessor of claim 1, wherein the condition further comprises: there are one or more other load instructions in the load queue that have not completed execution. ### Claim 10 (depends on 1) The microprocessor of claim 1, wherein the removal comprises an invalidation of the removed entry in response to an external snoop request that specifies the removal physical memory line address. ### Claim 11 (depends on 1) The microprocessor of claim 1, wherein the removal comprises a replacement of the copy of the line of memory at the removal physical memory line address by a fill of a copy of a line of memory at a fill physical memory line address into the removed entry of the second-level cache. ### Claim 12 (depends on 11) The microprocessor of claim 11, wherein microprocessor is further configured to: perform a fill of the copy of the line of memory at the fill physical memory line address into an entry of the first-level cache; wherein the snoop is performed: either after a removal from the first-level cache of the copy of the line of memory at the removal physical memory line address or in a first atomic manner with the removal from the first-level cache, wherein the first atomic manner is with respect to an ability of any load/store instruction to hit on the removed entry of the first-level cache; and either before a fill into the first-level cache of the copy of the line of memory at the fill physical memory line address or in a second atomic manner with the fill into the first-level cache, wherein the second atomic manner is with respect to an ability of any load/store instruction to hit on the filled entry of the first-level cache. ### Claim 13 (depends on 1) The microprocessor of claim 1, wherein the first-level cache is virtually-indexed and virtually-tagged; and wherein the second-level cache is physically-indexed and physically-tagged. ### Claim 14 (depends on 1) The microprocessor of claim 1, further comprising: wherein the microprocessor is configured to concurrently execute N load instructions, wherein N is greater than one; and wherein the load queue comprises a content-addressable memory (CAM) and has fewer than N CAM ports. ### Claim 15 A method, comprising: in a microprocessor comprising: a first-level cache and a second-level set associative cache that is inclusive of the first-level cache, wherein each entry of the second-level cache is uniquely identified by a set index and a way; a load queue, wherein each entry of the load queue is configured to hold: a load physical address proxy (PAP) for a load physical memory line address associated with a load instruction rather than holding the load physical memory line address itself, wherein the load PAP comprises the set index and the way that uniquely identifies the entry of the second-level cache that holds a copy of a line of memory specified by the load physical memory line address; and an indication of whether the load instruction has completed execution; performing a removal of a copy of a line of memory at a removal physical memory line address from an entry of the second-level cache; forming a removal PAP as a proxy for the removal physical memory line address, wherein the removal PAP comprises a set index and a way that uniquely identifies the removed entry; performing a snoop of the load queue with the removal PAP; and determining, based on the snoop, whether a condition is true, wherein the condition comprises: the removal PAP matches one or more load PAPs in one or more entries of the load queue associated with one or more load instructions that have completed execution; and if the condition is true, signaling an abort request. ### Claim 16 (depends on 15) The method of claim 15, wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions. ### Claim 17 (depends on 15) The method of claim 15, wherein a load instruction has completed execution when a load unit of the microprocessor has written a load PAP to an entry of the load queue associated with the load instruction. ### Claim 18 (depends on 17) The method of claim 17, further comprising: wherein each valid entry of the first-level cache holds a PAP of a physical memory line address of a cache line stored in the valid entry; and receiving, by the load unit during execution of the load instruction, a PAP from the first-level cache; and writing, by the load unit during execution of the load instruction, the PAP to the entry of the load queue associated with the load instruction and setting the indication that the load instruction has completed execution. ### Claim 19 (depends on 15) The method of claim 15, further comprising: determining, in response to the abort request, a flush boundary; and flushing at least all load instructions younger than the flush boundary. ### Claim 20 (depends on 19) The method of claim 19, wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has not completed execution. ### Claim 21 (depends on 20) The method of claim 20, further comprising: blocking dispatch, in response to the abort request, of load instructions until all load instructions older than the flush boundary have committed. ### Claim 22 (depends on 19) The method of claim 19, wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has completed execution and whose load PAP matches the removal PAP. ### Claim 23 (depends on 15) The method of claim 15, wherein the condition further comprises: there are one or more other load instructions in the load queue that have not completed execution. ### Claim 24 (depends on 15) The method of claim 15, wherein the removal comprises an invalidation of the removed entry in response to an external snoop request that specifies the removal physical memory line address. ### Claim 25 (depends on 15) The method of claim 15, wherein the removal comprises a replacement of the copy of the line of memory at the removal physical memory line address by a fill of a copy of a line of memory at a fill physical memory line address into the removed entry of the second-level cache. ### Claim 26 (depends on 25) The method of claim 25, further comprising: performing a fill of the copy of the line of memory at the fill physical memory line address into an entry of the first-level cache; wherein the snoop is performed: either after a removal from the first-level cache of the copy of the line of memory at the removal physical memory line address or in a first atomic manner with the removal from the first-level cache, wherein the first atomic manner is with respect to an ability of any load/store instruction to hit on the removed entry of the first-level cache; and either before a fill into the first-level cache of the copy of the line of memory at the fill physical memory line address or in a second atomic manner with the fill into the first-level cache, wherein the second atomic manner is with respect to an ability of any load/store instruction to hit on the filled entry of the first-level cache. ### Claim 27 (depends on 15) The method of claim 15, wherein the first-level cache is virtually-indexed and virtually-tagged; and wherein the second-level cache is physically-indexed and physically-tagged. ### Claim 28 (depends on 15) The method of claim 15, further comprising: wherein the microprocessor is configured to concurrently execute N load instructions, wherein N is greater than one; and wherein the load queue comprises a content-addressable memory (CAM) and has fewer than N CAM ports. ### Claim 29 A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising: a first-level cache and a second-level set associative cache that is inclusive of the first-level cache, wherein each entry of the second-level cache is uniquely identified by a set index and a way; a load queue, wherein each entry of the load queue is configured to hold: a load physical address proxy (PAP) for a load physical memory line address associated with a load instruction rather than holding the load physical memory line address itself, wherein the load PAP comprises the set index and the way that uniquely identifies the entry of the second-level cache that holds a copy of a line of memory specified by the load physical memory line address; and an indication of whether the load instruction has completed execution; wherein the microprocessor is configured to: perform a removal of a copy of a line of memory at a removal physical memory line address from an entry of the second-level cache; form a removal PAP as a proxy for the removal physical memory line address, wherein the removal PAP comprises a set index and a way that uniquely identifies the removed entry; perform a snoop of the load queue with the removal PAP; and determine, based on the snoop, whether a condition is true, wherein the condition comprises: the removal PAP matches one or more load PAPs in one or more entries of the load queue associated with one or more load instructions that have completed execution; and if the condition is true, signal an abort request.