# US 12,182,018 B2 · Instruction and micro-architecture support for decompression on core

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,182,018 B2
- Document ID: US12182018B2
- Status: Granted
- Kind: B2
- Application number: 17/133,615
- Filed: 2020-12-23
- Published: 2022-06-23
- Granted: 2024-12-31
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jayesh Gaur; Adarsh Chauhan; Vinodh Gopal; Vedvyas Shanbhogue; Sreenivas Subramoney; Wajdi Feghali
- Web page: https://patentgrep.com/patent/US12182018B2

## CPC

- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 9/3802: {Instruction prefetching}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 12/0862: with prefetch
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 2212/1024: Latency reduction
- G06F 2212/401: Compressed data
- G06F 2212/507: using speculative control
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

An apparatus comprising:
decode circuitry to decode a decompression instruction into a first micro operation and a second micro operation, wherein the first micro operation is to cause one or more load operations to fetch data into one or more cachelines of a cache of a processor core; and
Decompression Engine (DE) circuitry to decompress the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation, wherein the DE circuitry is to signal the processor core on completion of decompression of every cacheline.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the decompression instruction comprises a first operand to indicate a location of compressed data to be decompressed by the DE circuitry and a second operand to indicate a size of the compressed data to be decompressed by the DE circuitry.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the decompression instruction comprises a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored and a fourth operand to indicate a size of the decompressed data.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein one or more of the first operand and the third operand comprise a virtual memory address.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the second micro operation comprises a macro store operation to store the decompressed fetched data into the cache.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the cache of the processor core comprises a Level 2 (L2) cache.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein a consumer bitmap is to indicate which cacheline of the cache corresponds to consumer instructions after completion of decompression of the cacheline.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the processor core, DE circuitry, and the cache are on a single integrated circuit die.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the processor core comprises a Graphics Processing Unit (GPU) core.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the decompression instruction is to cause the DE circuitry to perform an out-of-order decompression of the one or more cachelines.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein each of the one or more cachelines are 64 Bytes.

### Claim 12

One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
decode a decompression instruction into a first micro operation and a second micro operation, wherein the first micro operation is to cause one or more load operations to fetch data into one or more cachelines of a cache of a processor core; and
cause Decompression Engine (DE) circuitry to decompress the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation, wherein the DE circuitry is to signal the processor core on completion of decompression of every cacheline.

### Claim 13 (depends on 12)

The one or more computer-readable media of claim 12, wherein the decompression instruction comprises a first operand to indicate a location of compressed data to be decompressed by the DE circuitry and a second operand to indicate a size of the compressed data to be decompressed by the DE circuitry.

### Claim 14 (depends on 13)

The one or more computer-readable media of claim 13, wherein the decompression instruction comprises a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored and a fourth operand to indicate a size of the decompressed data.

### Claim 15 (depends on 14)

The one or more computer-readable media of claim 14, wherein one or more of the first operand and the third operand comprise a virtual memory address.

### Claim 16 (depends on 12)

The one or more computer-readable media of claim 12, wherein the second micro operation comprises a macro store operation to store the decompressed fetched data into the cache.

### Claim 17 (depends on 12)

The one or more computer-readable media of claim 12, wherein the cache of the processor core comprises a Level 2 (L2) cache.

### Claim 18 (depends on 12)

The one or more computer-readable media of claim 12, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a consumer bitmap to indicate which cacheline of the cache corresponds to consumer instructions after completion of decompression of the cacheline.

### Claim 19 (depends on 12)

The one or more computer-readable media of claim 12, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DE circuitry to perform an out-of-order decompression of the one or more cachelines.

### Claim 20 (depends on 12)

The one or more computer-readable media of claim 12, wherein each of the one or more cachelines are 64 Bytes.

### Claim 21

A method comprising:
decoding a decompression instruction into a first micro operation and a second micro operation, wherein the first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core; and
causing Decompression Engine (DE) circuitry to decompress the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation, wherein the DE circuitry signals the processor core on completion of decompression of every cacheline.

### Claim 22 (depends on 21)

The method of claim 21, wherein the decompression instruction comprises a first operand to indicate a location of compressed data to be decompressed by the DE circuitry and a second operand to indicate a size of the compressed data to be decompressed by the DE circuitry.

### Claim 23 (depends on 22)

The method of claim 22, wherein the decompression instruction comprises a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored and a fourth operand to indicate a size of the decompressed data.

### Claim 24 (depends on 23)

The method of claim 23, wherein one or more of the first operand and the third operand comprise a virtual memory address.

### Claim 25 (depends on 21)

The method of claim 21, wherein the second micro operation comprises a macro store operation to store the decompressed fetched data into the cache.