# US 12,181,992 B1 · Intelligent riser testing device and methods

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- Number: US 12,181,992 B1
- Document ID: US12181992B1
- Status: Granted
- Kind: B1
- Application number: 17/963,334
- Filed: 2022-10-11
- Granted: 2024-12-31
- Earliest claimed: 2021-10-11
- Assignees: Sanblaze Technology, Inc.
- Applicants: SANBlaze Technology, Inc.
- Inventors: B. Vincent Asbridge; Ulf Frisk
- Web page: https://patentgrep.com/patent/US12181992B1

## CPC

- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A solution is the iRiser. The iRiser is a PCIe riser, designed to work with SANBlaze test systems but capable of operation in any PCIe slot on any computer. The iRiser includes a dedicated ASIC or programmed FPGA that cycles any of 32 signals, including power and reset, and samples power at up to 1 million samples per second, to any connected PCIe devices (such as sixteen NVMe drives under test in a SANBlaze test system, or more if larger testing systems are used). This allows precise insertion of any signal, including power and reset, at any desired testing point, and precise measurement of power drawn during any test condition, including transitions such as power on/off, reset, and low power state returning to running state. The iRiser can write measurement data to a host controller through direct memory access, providing the data synchronized to precise test conditions with zero overhead.

## Claims

### Claim 1

A method for device testing, comprising:
inserting a riser card into a host system between the host system and a device under test, wherein the device under test is connected through a peripheral component interconnect express (PCIe) connection;
controlling, by the riser card, a plurality of signals to the device under test, including power and reset signals, by turning on or off one or more general purpose input output pins on the riser card;
programmatically cycling, by the riser card, any of the plurality of signals to the device under test;
sampling, by the riser card, power to the device under test at up to one million samples per second by measuring voltage over a precision shunt resistor and processing through an analog to digital converter;
writing, by the riser card, the sampled power to host memory through direct memory access (DMA) such that the sampled power is accessible by the host system in synchronization with a specific test;
controlling power sampling by the host system setting specific bits into a control register of the riser card, including:
setting one bit in the control register that clears a specific memory buffer in host memory into which sampled power is written;
setting a second bit in the control register to select either continuous or fast mode, wherein both continuous and fast mode write into the specific memory buffer in host memory, and when an end of the buffer is reached: continuous mode wraps to a beginning of the buffer and continuous writing power samples into the buffer, while fast mode stops power sampling;
setting a third bit in the control register to select either normal or average sampling, wherein normal sampling writes every sample to memory buffer, while average sampling writes an average of consecutive samples to memory buffer; and
setting a fourth bit in the control register that enables or disables power sampling;
the host controlling tests by writing action commands to one or more action command registers or random access memory (RAM) on the riser card and specifying, within each action command:
specific pins to enable or disable signals sent from riser card to the device under test,
a counter specifying clock ticks until a next action, and
an address of a next action to perform; and
specifying a type in one of the action commands to control power sampling, including stop and start, instead of controlling specific pins.

### Claim 2

A method for device testing, comprising:
inserting a riser card into a host system between the host system and a device under test, wherein the device under test is connected through a peripheral component interconnect express (PCIe) connection;
controlling, by the riser card, a plurality of signals to the device under test including power and reset signals;
programmatically cycling, by the riser card, any of the plurality of signals to the device under test;
sampling, by the riser card, power to the device under test at up to one million samples per second by measuring voltage over a precision shunt resistor and processing through an analog to digital converter;
writing, by the riser card, the sampled power to host memory through direct memory access (DMA) such that the sampled power is accessible by the host system in synchronization with a specific test; and
controlling power sampling by the host system setting specific bits into a control register of the riser card.

### Claim 3 (depends on 2)

The method of claim 2, further comprising the host system setting a bit in the control register that clears a specific memory buffer in host memory into which sampled power is written.

### Claim 4 (depends on 3)

The method of claim 3, further comprising the host system setting a bit in the control register to select either continuous or fast mode, wherein both continuous and fast mode write into the specific memory buffer in host memory, and when an end of the buffer is reached: continuous mode wraps to a beginning of the buffer and continuous writing power samples into the buffer, while fast mode stops power sampling.

### Claim 5 (depends on 3)

The method of claim 3, further comprising the host system setting a bit in the control register to select either normal or average sampling, wherein normal sampling writes every sample to memory buffer, while average sampling writes an average of consecutive samples to memory buffer.

### Claim 6 (depends on 2)

The method of claim 2, further comprising the host system setting a bit in the control register that enables or disables power sampling.

### Claim 7 (depends on 2)

The method of claim 2, wherein controlling the plurality of signals to the device under test further comprises turning on or off one or more general purpose input output pins on the riser card.

### Claim 8 (depends on 7)

The method of claim 7, further comprising the host controlling tests by writing action commands to one or more action command registers or random access memory (RAM) on the riser card.

### Claim 9 (depends on 8)

The method of claim 8, further comprising specifying, within each action command, specific pins to enable or disable signals sent from riser card to the device under test, a counter specifying clock ticks until a next action, and an address of a next action to perform.

### Claim 10 (depends on 9)

The method of claim 9, further comprising specifying a type in one of the action commands to control power sampling including stop and start, instead of controlling specific pins.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
the host system setting a glitch bit in one of the action commands;
detecting the glitch bit by the riser card;
loading the action as normal;
reverting signals to a prior state from before the action when the counter expires; and
processing the next action.