# US 12,181,990 B2 · Fail-safe boot block to dynamically boot platform resiliency firmware > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,990 B2 - Document ID: US12181990B2 - Status: Granted - Kind: B2 - Application number: 18/192,529 - Filed: 2023-03-29 - Published: 2024-10-03 - Granted: 2024-12-31 - Earliest claimed: 2023-03-29 - Assignees: Dell Products L.P. - Applicants: Dell Products L.P. - Inventors: Shekar Babu Suryanarayana; Ibrahim Sayyed - Web page: https://patentgrep.com/patent/US12181990B2 ## CPC - G06F 11/2284: {by power-on test, e.g. power-on self test [POST]} - G06F 11/2273: {Test methods} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A disclosed fail-safe boot block method leverages embedded controller (EC) functionality to monitor power on self-test (POST) messages and, in response to detecting a POST error message, execute a sequence of main basic input/output system (BIOS) recovery operations including, in at least some embodiments, performing top-block swap recovery features supported by the platform. If the main BIOS recovery operations fail to resolve the POST error issue, e.g., fail to resolve a No Boot/No Post/No Video (NB/NP/NV) state of the platform, a resiliency boot block bit is set and a reset is executed to boot the platform, via a fail-safe boot block, into the safe BIOS mode for error analysis and corrective action. The fail safe boot block and the safe BIOS firmware may reside in a flash partition that is factory-programmed and sealed to prevent substantially any subsequent programming and/or of the storage device. Additional benefit of the fail-safe boot features are disclosed herein. ## Claims ### Claim 1 A method comprising: monitoring power on self-test (POST) messages of an information handling system; responsive to detecting a POST error message indicative of a POST error condition, executing a recovery sequence comprising a sequence of main basic input/output system (BIOS) recovery operations; responsive to determining the recovery sequence did not resolve the POST error condition, setting a resiliency boot block bit; executing a reset to boot the information handling system to a safe BIOS mode to determine a failure stage of the main BIOS; and taking corrective action based on the failure stage. ### Claim 2 (depends on 1) The method of claim 1, wherein the monitoring is performed by an embedded controller (EC) of the information handling system. ### Claim 3 (depends on 1) The method of claim 1, wherein the main BIOS recovery operations include at least one of: a memory built in self-test (MBIST) operation, a single bit serial peripheral interface (SPI) operation, and a top-block swap boot partition switch operation. ### Claim 4 (depends on 1) The method of claim 1, wherein determining the failure stage of the main BIOS includes: activating a unified extensible firmware interface (UEFI) telemetry program to obtain BIOS attribute data. ### Claim 5 (depends on 1) The method of claim 1, wherein taking corrective action includes at least one of: responsive to detecting a corrupted driver execution environment (DXE) driver, fetching a latest BIOS from a cloud-based store; responsive to a runtime memory mapping handoff error, sending telemetry to a cloud store and requesting a memory module dispatch; and responsive to determining a hardware issue with an SPI device, sending telemetry to a cloud store and requesting a motherboard dispatch. ### Claim 6 An information handling system, comprising: a central processing unit (CPU); an embedded controller (EC); and a computer readable memory, accessible to the processor, including processor executable instructions that, when executed by the CPU, cause the system to perform operations including: monitoring power on self-test (POST) messages of an information handling system; responsive to detecting a POST error message indicative of a POST error condition, executing a recovery sequence comprising a sequence of main basic input/output system (BIOS) recovery operations; responsive to determining the recovery sequence did not resolve the POST error condition, setting a resiliency boot block bit; executing a reset to boot the information handling system to a safe BIOS mode to determine a failure stage of the main BIOS; and taking corrective action based on the failure stage. ### Claim 7 (depends on 6) The information handling system of claim 6, wherein the monitoring is performed by the EC of the information handling system. ### Claim 8 (depends on 6) The information handling system of claim 6, wherein the main BIOS recovery operations include at least one of: a memory built in self-test (MBIST) operation, a single bit serial peripheral interface (SPI) operation, and a top-block swap boot partition switch operation. ### Claim 9 (depends on 6) The information handling system of claim 6, wherein determining the failure stage of the main BIOS includes: activating a unified extensible firmware interface (UEFI) telemetry program to obtain BIOS attribute data. ### Claim 10 (depends on 6) The information handling system of claim 6, wherein taking corrective action includes at least one of: responsive to detecting a corrupted driver execution environment (DXE) driver, fetching a latest BIOS from a cloud-based store; responsive to a runtime memory mapping handoff error, sending telemetry to a cloud store and requesting a memory module dispatch; and responsive to determining a hardware issue with an SPI device, sending telemetry to a cloud store and requesting a motherboard dispatch. ### Claim 11 A non-transitory computer readable medium including processor executable instructions that, when executed by a processor of an information handling system, cause the information handling system to perform operations including: monitoring power on self-test (POST) messages of the information handling system; responsive to detecting a POST error message indicative of a POST error condition, executing a recovery sequence comprising a sequence of main basic input/output system (BIOS) recovery operations; responsive to determining the recovery sequence did not resolve the POST error condition, setting a resiliency boot block bit; executing a reset to boot the information handling system to a safe BIOS mode to determine a failure stage of the main BIOS; and taking corrective action based on the failure stage. ### Claim 12 (depends on 11) The non-transitory computer readable medium of claim 11, wherein the monitoring is performed by an embedded controller (EC) of the information handling system. ### Claim 13 (depends on 11) The non-transitory computer readable medium of claim 11, wherein the main BIOS recovery operations include at least one of: a memory built in self-test (MBIST) operation, a single bit serial peripheral interface (SPI) operation, and a top-block swap boot partition switch operation. ### Claim 14 (depends on 11) The non-transitory computer readable medium of claim 11, wherein determining the failure stage of the main BIOS includes: activating a unified extensible firmware interface (UEFI) telemetry program to obtain BIOS attribute data. ### Claim 15 (depends on 11) The non-transitory computer readable medium of claim 11, wherein taking corrective action includes at least one of: responsive to detecting a corrupted driver execution environment (DXE) driver, fetching a latest BIOS from a cloud-based store; responsive to a runtime memory mapping handoff error, sending telemetry to a cloud store and requesting a memory module dispatch; and responsive to determining a hardware issue with an SPI device, sending telemetry to a cloud store and requesting a motherboard dispatch.