# US 12,181,987 B2 · HBM RAS cache architecture

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- Number: US 12,181,987 B2
- Document ID: US12181987B2
- Status: Granted
- Kind: B2
- Application number: 17/499,852
- Filed: 2021-10-12
- Published: 2022-02-03
- Granted: 2024-12-31
- Earliest claimed: 2018-07-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dimin Niu; Krishna Malladi; Hongzhong Zheng
- Web page: https://patentgrep.com/patent/US12181987B2

## CPC

- G06F 11/2094: {Redundant storage or storage space (G06F11/2056 takes precedence)}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 29/4401: {for self repair}
- G11C 29/74: {using duplex memories, i.e. using dual copies}
- G11C 29/76: {using address translation or modifications}
- G06F 2201/82: Solving problems relating to consistency
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

## Claims

### Claim 1

An apparatus comprising:
a first device comprising:
a memory cell die configured to store data based, at least in part, on a memory address; and
a logic die comprising:
an interface to the memory cell die, wherein the interface is configured to communicate a memory access to the memory cell die; and
a second device configured to send a memory address associated with an error;
wherein the logic die is configured to:
receive, from the second device, the memory address;
based on a status of the second device, map the memory address to a portion of a spare memory, wherein the status of the second device is engaged with a client; and
based on a memory access to the memory cell die, determine that the memory access is associated with the error, and complete the memory access with, at least in part, the portion of the spare memory.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory address associated with the error is stored in an address data structure comprising:
an error correction code portion to protect against errors in the address-data structure, and
a valid indicator configured to indicate an active status of the memory address.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the logic die is configured to:
receive a write memory access for data at a memory address;
determine that the memory address is associated with an error; and
write the data to the portion of the spare memory.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the memory address associated with the error is stored in an address-data structure, and the logic die is configured to determine that the memory address is associated with an error by:
determining that the memory address is stored within the address data structure as a memory address entry, and
determining that a valid indicator indicates that the memory address entry is active.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the logic die is configured to:
receive a read memory access for data at a memory address;
determine that the memory address is associated with an error; and
retrieve the data from a portion of the spare memory.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the memory address associated with the error is stored in an address data structure, and the logic die is configured to:
receive a message indicating that a memory address is associated with an error;
place the memory address in the address data structure; and
associate the memory address with the portion of the spare memory.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the logic die is configured to receive a message indicating that a memory address is associated with an error by:
receiving a write memory access to a predefined memory address, wherein the predefined memory address is associated with the address data structure.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the logic die is configured to:
monitor a usage level of the spare memory; and
provide an indicator of the usage level of the spare memory.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the logic die is configured to provide, based on an operational status of the first device, information about an address mapping operation of the logic die.

### Claim 10

A method for memory error management, the method comprising:
determining, by a processing device, based on a first access of a memory device comprising a memory die and a logic die, an error associated with a portion of the memory die;
sending, from the processing device to the logic die, based on the determining, a first indication of the error associated with the portion of the memory die;
sending, from the processing device, to a driver for the processing device, based on the determining, a second indication of the error associated with the portion of the memory die, wherein the second indication indicates a memory address associated with the error;
storing, by the driver, in a data structure, the memory address associated with the error;
sending, from the processing device to the logic die, a second access of the portion of the memory die; and
performing, by a reliability circuit, based on the first indication, the second access using at least a portion of a spare memory.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first indication comprises an address associated with the portion of the memory die.

### Claim 12 (depends on 11)

The method of claim 11, further comprising mapping, by the reliability circuit, the address associated with the portion of the memory die to the portion of the spare memory.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the second access comprises a write access; and
performing the second access comprises writing data associated with the write access to the portion of the spare memory based on the mapping.

### Claim 14 (depends on 12)

The method of claim 12, wherein:
the second access comprises a read access; and
performing the second access comprises reading data associated with the read access from the portion of the spare memory based on the mapping.

### Claim 15 (depends on 11)

The method of claim 11, further comprising storing the address in a non-volatile memory.

### Claim 16 (depends on 10)

The method of claim 10, wherein the first device comprises a host device.

### Claim 17 (depends on 10)

The method of claim 10, wherein the reliability circuit is disposed on a logic die.

### Claim 18

An apparatus comprising:
a first device comprising a logic die comprising:
a first interface to a memory die, wherein the memory die is configured to store data based on a memory address;
a second interface configured to communicate memory accesses for the memory die; and
a spare memory configured to store data;
wherein the logic die is configured to:
receive, from a second device, a memory address associated with an error;
map the memory address associated with the error to a portion of the spare memory;
store the memory address in an address data structure comprising an error correction code portion for errors in the address data structure;
based on a memory access to the memory die, determine that the memory access is associated with the error, and complete the memory access with, at least in part, the portion of the spare memory; and
provide, to the second device, an indication of a capacity of the spare memory.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the logic die is configured to:
receive a write memory access for data at the memory address;
determine that the memory address is associated with the error; and
write the data to a portion of the spare memory.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the logic die is configured to:
receive a read memory access for data at the memory address;
determine that the memory address is associated with the error; and
retrieve the data from a mapped portion of the spare memory.